// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/clock/rv1126-cru.h>
#include <dt-bindings/power/rv1126-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include "rv1126-dram-default-timing.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "rockchip,rv1126";

	interrupt-parent = <&gic>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		spi0 = &spi0;
		spi1 = &spi1;
		dphy0 = &csi_dphy0;
		dphy1 = &csi_dphy1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu1: cpu@f01 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu2: cpu@f02 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf02>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};

		cpu3: cpu@f03 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf03>;
			enable-method = "psci";
			clocks = <&cru ARMCLK>;
			operating-points-v2 = <&cpu0_opp_table>;
		};
	};

	cpu0_opp_table: cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-408000000 {
			opp-hz = /bits/ 64 <408000000>;
			opp-microvolt = <800000 800000 945000>;
			clock-latency-ns = <40000>;
			opp-suspend;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			opp-microvolt = <800000 800000 945000>;
			clock-latency-ns = <40000>;
		};
		opp-816000000 {
			opp-hz = /bits/ 64 <816000000>;
			opp-microvolt = <800000 800000 945000>;
			clock-latency-ns = <40000>;
		};
		opp-1008000000 {
			opp-hz = /bits/ 64 <1008000000>;
			opp-microvolt = <800000 800000 945000>;
			clock-latency-ns = <40000>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	display_subsystem: display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vop_out>;
		status = "disabled";

		route {
			route_dsi: route-dsi {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <&vop_out_dsi>;
			};

			route_rgb: route-rgb {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <&vop_out_rgb>;
			};
		};
	};

	fiq_debugger: fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,wake-irq = <0>;
		rockchip,irq-mode-enable = <0>;
		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	mpp_srv: mpp-srv {
		compatible = "rockchip,mpp-service";
		rockchip,taskqueue-count = <3>;
		rockchip,resetgroup-count = <3>;
		status = "disabled";
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	rgb: rgb {
		compatible = "rockchip,rv1126-rgb";
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				rgb_in_vop: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vop_out_rgb>;
				};
			};

		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	grf: syscon@fe000000 {
		compatible = "rockchip,rv1126-grf", "syscon";
		reg = <0xfe000000 0x20000>;
	};

	pmugrf: syscon@fe020000 {
		compatible = "rockchip,rv1126-pmugrf", "syscon";
		reg = <0xfe020000 0x1000>;

		pmu_io_domains: io-domains {
			compatible = "rockchip,rv1126-pmu-io-voltage-domain";
		};
	};

	qos_usb_host: qos@fe810008 {
		compatible = "syscon";
		reg = <0xfe810008 0x20>;
	};

	qos_usb_otg: qos@fe810088 {
		compatible = "syscon";
		reg = <0xfe810088 0x20>;
	};

	qos_npu: qos@fe850008 {
		compatible = "syscon";
		reg = <0xfe850008 0x20>;
	};

	qos_emmc: qos@fe860008 {
		compatible = "syscon";
		reg = <0xfe860008 0x20>;
	};

	qos_nandc: qos@fe860088 {
		compatible = "syscon";
		reg = <0xe860088 0x20>;
	};

	qos_sfc: qos@fe860208 {
		compatible = "syscon";
		reg = <0xfe860208 0x20>;
	};

	qos_sdmmc: qos@fe868008 {
		compatible = "syscon";
		reg = <0xfe868008  0x20>;
	};

	qos_sdio: qos@fe86c008 {
		compatible = "syscon";
		reg = <0xfe86c008 0x20>;
	};

	qos_vepu_rd0: qos@fe870008 {
		compatible = "syscon";
		reg = <0xfe870008 0x20>;
	};

	qos_vepu_rd1: qos@fe870088 {
		compatible = "syscon";
		reg = <0xfe870088 0x20>;
	};

	qos_vepu_wr: qos@fe870108 {
		compatible = "syscon";
		reg = <0xfe870108 0x20>;
	};

	qos_ispp_m0: qos@fe880018 {
		compatible = "syscon";
		reg = <0xfe880018 0x20>;
	};

	qos_ispp_m1: qos@fe880098 {
		compatible = "syscon";
		reg = <0xfe880098 0x20>;
	};

	qos_isp: qos@fe890008 {
		compatible = "syscon";
		reg = <0xfe890008 0x20>;
	};

	qos_cif_lite: qos@fe890088 {
		compatible = "syscon";
		reg = <0xfe890088 0x20>;
	};

	qos_cif: qos@fe890108 {
		compatible = "syscon";
		reg = <0xfe890108 0x20>;
	};

	qos_iep: qos@fe8a0008 {
		compatible = "syscon";
		reg = <0xfe8a0008 0x20>;
	};

	qos_rga_rd: qos@fe8a0088 {
		compatible = "syscon";
		reg = <0xfe8a0088 0x20>;
	};

	qos_rga_wr: qos@fe8a0108 {
		compatible = "syscon";
		reg = <0xfe8a0108 0x20>;
	};

	qos_vop: qos@fe8a0188 {
		compatible = "syscon";
		reg = <0xfe8a0188 0x20>;
	};

	qos_vdpu: qos@fe8b0008 {
		compatible = "syscon";
		reg = <0xfe8b0008 0x20>;
	};

	gic: interrupt-controller@feff0000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;

		reg = <0xfeff1000 0x1000>,
		      <0xfeff2000 0x2000>,
		      <0xfeff4000 0x2000>,
		      <0xfeff6000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	pvtm@ff040000 {
		compatible = "rockchip,rv1126-cpu-pvtm";
		reg = <0xff040000 0x100>;
		clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>;
		clock-names = "clk", "pclk";
		resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>;
		reset-names = "clk", "pclk";
	};

	pmu: power-management@ff3e0000 {
		compatible = "rockchip,rv1126-pmu", "syscon";
		reg = <0xff3e0000 0x1000>;

		power: power-controller {
			compatible = "rockchip,rv1126-power-controller";
			#power-domain-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			/* These power domains are grouped by VD_NPU */
			pd_npu@RV1126_PD_NPU {
				reg = <RV1126_PD_NPU>;
				clocks = <&cru ACLK_NPU>,
					 <&cru HCLK_NPU>,
					 <&cru PCLK_PDNPU>,
					 <&cru CLK_CORE_NPU>;
				pm_qos = <&qos_npu>;
			};
			/* These power domains are grouped by VD_VEPU */
			pd_vepu@RV1126_PD_VEPU {
				reg = <RV1126_PD_VEPU>;
				clocks = <&cru ACLK_VENC>,
					 <&cru HCLK_VENC>,
					 <&cru CLK_VENC_CORE>;
				pm_qos = <&qos_vepu_rd0>,
					 <&qos_vepu_rd1>,
					 <&qos_vepu_wr>;
			};
			/* These power domains are grouped by VD_LOGIC */
			pd_vi@RV1126_PD_VI {
				reg = <RV1126_PD_VI>;
				clocks = <&cru ACLK_ISP>,
					 <&cru HCLK_ISP>,
					 <&cru CLK_ISP>,
					 <&cru ACLK_CIF>,
					 <&cru HCLK_CIF>,
					 <&cru DCLK_CIF>,
					 <&cru CLK_CIF_OUT>,
					 <&cru CLK_MIPICSI_OUT>,
					 <&cru PCLK_CSIHOST>,
					 <&cru ACLK_CIFLITE>,
					 <&cru HCLK_CIFLITE>,
					 <&cru DCLK_CIFLITE>;
				pm_qos = <&qos_isp>,
					 <&qos_cif_lite>,
					 <&qos_cif>;
			};
			pd_vo@RV1126_PD_VO {
				reg = <RV1126_PD_VO>;
				clocks = <&cru ACLK_RGA>,
					 <&cru HCLK_RGA>,
					 <&cru CLK_RGA_CORE>,
					 <&cru ACLK_VOP>,
					 <&cru HCLK_VOP>,
					 <&cru DCLK_VOP>,
					 <&cru PCLK_DSIHOST>,
					 <&cru ACLK_IEP>,
					 <&cru HCLK_IEP>,
					 <&cru CLK_IEP_CORE>;
				pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
					 <&qos_vop>, <&qos_iep>;
			};
			pd_ispp@RV1126_PD_ISPP {
				reg = <RV1126_PD_ISPP>;
				clocks = <&cru ACLK_ISPP>,
					 <&cru HCLK_ISPP>,
					 <&cru CLK_ISPP>;
				pm_qos = <&qos_ispp_m0>,
					 <&qos_ispp_m1>;
			};
			pd_vdpu@RV1126_PD_VDPU {
				reg = <RV1126_PD_VDPU>;
				clocks = <&cru ACLK_VDEC>,
					 <&cru HCLK_VDEC>,
					 <&cru CLK_VDEC_CORE>,
					 <&cru CLK_VDEC_CA>,
					 <&cru CLK_VDEC_HEVC_CA>,
					 <&cru ACLK_JPEG>,
					 <&cru HCLK_JPEG>;
				pm_qos = <&qos_vdpu>;
			};
			pd_nvm@RV1126_PD_NVM {
				reg = <RV1126_PD_NVM>;
				clocks = <&cru HCLK_EMMC>,
					 <&cru CLK_EMMC>,
					 <&cru HCLK_NANDC>,
					 <&cru CLK_NANDC>,
					 <&cru HCLK_SFC>,
					 <&cru HCLK_SFCXIP>,
					 <&cru SCLK_SFC>;
				pm_qos = <&qos_emmc>,
					 <&qos_nandc>,
					 <&qos_sfc>,
					 <&qos_sdmmc>;
			};
			pd_sdio@RV1126_PD_SDIO {
				reg = <RV1126_PD_SDIO>;
				clocks = <&cru HCLK_SDIO>,
					 <&cru CLK_SDIO>;
				pm_qos = <&qos_sdio>;
			};
			pd_usb@RV1126_PD_USB {
				reg = <RV1126_PD_USB>;
				clocks = <&cru HCLK_USBHOST>,
					 <&cru HCLK_USBHOST_ARB>,
					 <&cru CLK_USBHOST_UTMI_OHCI>,
					 <&cru ACLK_USBOTG>,
					 <&cru CLK_USBOTG_REF>;
				pm_qos = <&qos_usb_host>,
					 <&qos_usb_otg>;
			};
		};
	};

	i2c0: i2c@ff3f0000 {
		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
		reg = <0xff3f0000 0x1000>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		status = "disabled";
	};

	i2c2: i2c@ff400000 {
		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
		reg = <0xff400000 0x1000>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_xfer>;
		status = "disabled";
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dmac: dma-controller@ff4e0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xff4e0000 0x4000>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&cru ACLK_DMAC>;
			clock-names = "apb_pclk";
		};
	};

	uart1: serial@ff410000 {
		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
		reg = <0xff410000 0x100>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac 7>, <&dmac 6>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
		status = "disabled";
	};

	pwm0: pwm@ff430000 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff430000 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm0m0_pins>;
		clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm1: pwm@ff430010 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff430010 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm1m0_pins>;
		clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm2: pwm@ff430020 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff430020 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm2m0_pins>;
		clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm3: pwm@ff430030 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff430030 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm3m0_pins>;
		clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm4: pwm@ff440000 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff440000 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm4m0_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm5: pwm@ff440010 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff440010 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm5m0_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm6: pwm@ff440020 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff440020 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm6m0_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm7: pwm@ff440030 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff440030 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm7m0_pins>;
		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	spi0: spi@ff450000 {
		compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi";
		reg = <0xff450000 0x1000>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac 1>, <&dmac 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi0m0_clk &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso &spi0m0_mosi>;
		pinctrl-1 = <&spi0m0_clk_hs &spi0m0_cs0n &spi0m0_cs1n &spi0m0_miso_hs &spi0m0_mosi_hs>;
		status = "disabled";
	};

	pvtm@ff470000 {
		compatible = "rockchip,rv1126-pmu-pvtm";
		reg = <0xff470000 0x100>;
		clocks = <&pmucru CLK_PMUPVTM>, <&pmucru PCLK_PMUPVTM>;
		clock-names = "clk", "pclk";
		resets = <&cru SRST_PMUPVTM>, <&cru SRST_PMUPVTM_P>;
		reset-names = "clk", "pclk";
	};

	pmucru: clock-controller@ff480000 {
		compatible = "rockchip,rv1126-pmucru";
		reg = <0xff480000 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cru: clock-controller@ff490000 {
		compatible = "rockchip,rv1126-cru";
		reg = <0xff490000 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		assigned-clocks =
			<&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
			<&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
			<&cru PLL_HPLL>, <&cru ARMCLK>,
			<&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
			<&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
			<&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
			<&cru HCLK_PDCORE_NIU>;
		assigned-clock-rates =
			<32768>, <1188000000>,
			<100000000>, <1000000000>,
			<1600000000>, <600000000>,
			<500000000>, <200000000>,
			<100000000>, <300000000>,
			<200000000>, <150000000>,
			<200000000>;
		assigned-clock-parents =
			<&pmucru CLK_OSC0_DIV32K>;
	};

	csi_dphy0: csi-dphy@ff4b0000 {
		compatible = "rockchip,rv1126-csi-dphy";
		reg = <0xff4b0000 0x8000>;
		clocks = <&cru PCLK_CSIPHY0>;
		clock-names = "pclk";
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	csi_dphy1: csi-dphy@ff4b8000 {
		compatible = "rockchip,rv1126-csi-dphy";
		reg = <0xff4b8000 0x8000>;
		clocks = <&cru PCLK_CSIPHY1>;
		clock-names = "pclk";
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	u2phy0: usb2-phy@ff4c0000 {
		compatible = "rockchip,rv1126-usb2phy";
		reg = <0xff4c0000 0x8000>;
		clocks = <&cru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>;
		clock-names = "phyclk", "pclk";
		resets = <&cru SRST_USBPHYPOR_OTG>, <&cru SRST_USBPHY_OTG_P>;
		reset-names = "u2phy", "u2phy-apb";
		#clock-cells = <0>;
		clock-output-names = "usb480m_phy0";
		status = "disabled";

		u2phy_otg: otg-port {
			#phy-cells = <0>;
			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "otg-bvalid", "otg-id",
					  "linestate", "disconnect";
			status = "disabled";
		};
	};

	u2phy1: usb2-phy@ff4c8000 {
		compatible = "rockchip,rv1126-usb2phy";
		reg = <0xff4c8000 0x8000>;
		clocks = <&cru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>;
		clock-names = "phyclk", "pclk";
		resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>;
		reset-names = "u2phy", "u2phy-apb";
		#clock-cells = <0>;
		clock-output-names = "usb480m_phy1";
		status = "disabled";

		u2phy_host: host-port {
			#phy-cells = <0>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "linestate", "disconnect";
			status = "disabled";
		};
	};

	mipi_dphy: mipi-dphy@ff4d0000 {
		compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy";
		reg = <0xff4d0000 0x500>;
		clocks = <&cru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>;
		clock-names = "ref", "pclk";
		clock-output-names = "mipi_dphy_pll";
		#clock-cells = <0>;
		resets = <&cru SRST_DSIPHY_P>;
		reset-names = "apb";
		#phy-cells = <0>;
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	crypto: crypto@ff500000 {
		compatible = "rockchip,rv1126-crypto";
		reg = <0xff500000 0x10000>;
		clock-names = "sclk_crypto", "sclk_crypto_apk";
		clocks = <&cru CLK_CRYPTO_CORE>, <&cru CLK_CRYPTO_PKA>;
		clock-frequency = <200000000>, <300000000>;
		status = "disabled";
	};

	i2c1: i2c@ff510000 {
		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
		reg = <0xff510000 0x1000>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		status = "disabled";
	};

	i2c3: i2c@ff520000 {
		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
		reg = <0xff520000 0x1000>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3m0_xfer>;
		status = "disabled";
	};

	i2c4: i2c@ff530000 {
		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
		reg = <0xff530000 0x1000>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4m0_xfer>;
		status = "disabled";
	};

	i2c5: i2c@ff540000 {
		compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
		reg = <0xff540000 0x1000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
		clock-names = "i2c", "pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c5m0_xfer>;
		status = "disabled";
	};

	pwm8: pwm@ff550000 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff550000 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm8m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm9: pwm@ff550010 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff550010 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm9m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm10: pwm@ff550020 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff550020 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm10m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm11: pwm@ff550030 {
		compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
		reg = <0xff550030 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm11m0_pins>;
		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	uart0: serial@ff560000 {
		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
		reg = <0xff560000 0x100>;
		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac 5>, <&dmac 4>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
		status = "disabled";
	};

	uart2: serial@ff570000 {
		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
		reg = <0xff570000 0x100>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac 9>, <&dmac 8>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart2m1_xfer>;
		status = "disabled";
	};

	uart3: serial@ff580000 {
		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
		reg = <0xff580000 0x100>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac 11>, <&dmac 10>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart3m0_xfer &uart3m0_ctsn &uart3m0_rtsn>;
		status = "disabled";
	};

	uart4: serial@ff590000 {
		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
		reg = <0xff590000 0x100>;
		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac 13>, <&dmac 12>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>;
		status = "disabled";
	};

	uart5: serial@ff5a0000 {
		compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
		reg = <0xff5a0000 0x100>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		dmas = <&dmac 15>, <&dmac 14>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
		status = "disabled";
	};

	spi1: spi@ff5b0000 {
		compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi";
		reg = <0xff5b0000 0x1000>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac 3>, <&dmac 2>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi1m0_clk &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso &spi1m0_mosi>;
		pinctrl-1 = <&spi1m0_clk_hs &spi1m0_cs0n &spi1m0_cs1n &spi1m0_miso_hs &spi1m0_mosi_hs>;
		status = "disabled";
	};

	otp: otp@ff5c0000 {
		compatible = "rockchip,rv1126-otp";
		reg = <0xff5c0000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&cru CLK_OTP>, <&cru PCLK_OTP>;
		clock-names = "otp", "apb_pclk";
		status = "disabled";

		/* Data cells */
		otp_id: id@7 {
			reg = <0x07 0x10>;
		};
		cpu_leakage: cpu-leakage@17 {
			reg = <0x17 0x1>;
		};
		logic_leakage: logic-leakage@18 {
			reg = <0x18 0x1>;
		};
		npu_leakage: npu-leakage@19 {
			reg = <0x19 0x1>;
		};
	};

	secure_otp: secure_otp@0xff5d0000 {
		compatible = "rockchip,rv1126-secure-otp";
		reg = <0xff5d0000 0x4000>;
		secure_conf = <0xfe0a0008>;
	};

	saradc: saradc@ff5e0000 {
		compatible = "rockchip,rk3399-saradc";
		reg = <0xff5e0000 0x100>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		#io-channel-cells = <1>;
		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
		clock-names = "saradc", "apb_pclk";
		resets = <&cru SRST_SARADC_P>;
		reset-names = "saradc-apb";
		status = "disabled";
	};

	cpu_tsadc: tsadc@ff5f0000 {
		compatible = "rockchip,rv1126-tsadc";
		reg = <0xff5f0000 0x100>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		assigned-clocks = <&cru CLK_CPU_TSADC>;
		assigned-clock-rates = <600000>;
		clocks = <&cru CLK_CPU_TSADC>, <&cru PCLK_CPU_TSADC>,
			 <&cru CLK_CPU_TSADCPHY>;
		clock-names = "tsadc", "apb_pclk", "phy_clk";
		resets = <&cru SRST_CPU_TSADC_P>, <&cru SRST_CPU_TSADC>,
			 <&cru SRST_CPU_TSADCPHY>;
		reset-names = "tsadc-apb", "tsadc", "tsadc-phy";
		rockchip,hw-tshut-temp = <120000>;
		#thermal-sensor-cells = <1>;
		status = "disabled";
	};

	npu_tsadc: tsadc@ff5f8000 {
		compatible = "rockchip,rv1126-tsadc";
		reg = <0xff5f8000 0x100>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
		assigned-clocks = <&cru CLK_NPU_TSADC>;
		assigned-clock-rates = <600000>;
		clocks = <&cru CLK_NPU_TSADC>, <&cru PCLK_NPU_TSADC>,
			 <&cru CLK_NPU_TSADCPHY>;
		clock-names = "tsadc", "apb_pclk", "phy_clk";
		resets = <&cru SRST_NPU_TSADC_P>, <&cru SRST_NPU_TSADC>,
			 <&cru SRST_NPU_TSADCPHY>;
		reset-names = "tsadc-apb", "tsadc", "tsadc-phy";
		rockchip,hw-tshut-temp = <120000>;
		#thermal-sensor-cells = <1>;
		status = "disabled";
	};

	can: can@ff610000 {
		compatible = "rockchip,can-1.0";
		reg = <0xff610000 0x100>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		assigned-clocks = <&cru CLK_CAN>;
		assigned-clock-rates = <100000000>;
		clocks = <&cru CLK_CAN>, <&cru PCLK_CAN>;
		clock-names = "baudclk", "apb_pclk";
		resets = <&cru SRST_CAN>, <&cru SRST_CAN_P>;
		reset-names = "can", "can-apb";
		status = "disabled";
	};

	wdt: watchdog@ff680000 {
		compatible = "rockchip,rv1126-wdt", "snps,dw-wdt";
		reg = <0xff680000 0x100>;
		clocks = <&cru PCLK_WDT>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	mailbox: mailbox@ff6a0000 {
		compatible = "rockchip,rv1126-mailbox",
			     "rockchip,rk3368-mailbox";
		reg = <0xff6a0000 0x1000>;
		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_MAILBOX>;
		clock-names = "pclk_mailbox";
		#mbox-cells = <1>;
		status = "disabled";
	};

	hw_decompress: decompress@ff6c0000 {
		compatible = "rockchip,hw-decompress";
		reg = <0xff6c0000 0x10000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
		clock-names = "aclk", "dclk", "pclk";
		soft-reset-addr = <0xff490314>;
		status = "disabled";
	};

	i2s0_8ch: i2s@ff800000 {
		compatible = "rockchip,rv1126-i2s-tdm";
		reg = <0xff800000 0x1000>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <&dmac 20>, <&dmac 19>;
		dma-names = "tx", "rx";
		resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>;
		reset-names = "tx-m", "rx-m";
		rockchip,cru = <&cru>;
		rockchip,grf = <&grf>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0m0_sclk_tx
			     &i2s0m0_sclk_rx
			     &i2s0m0_lrck_tx
			     &i2s0m0_lrck_rx
			     &i2s0m0_sdi0
			     &i2s0m0_sdo0
			     &i2s0m0_sdo1_sdi3
			     &i2s0m0_sdo2_sdi2
			     &i2s0m0_sdo3_sdi1>;
		status = "disabled";
	};

	i2s1_2ch: i2s@ff810000 {
		compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s";
		reg = <0xff810000 0x1000>;
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S1>, <&cru HCLK_I2S1>;
		clock-names = "i2s_clk", "i2s_hclk";
		dmas = <&dmac 22>, <&dmac 21>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1m0_sclk
			     &i2s1m0_lrck
			     &i2s1m0_sdi
			     &i2s1m0_sdo>;
		status = "disabled";
	};

	i2s2_2ch: i2s@ff820000 {
		compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s";
		reg = <0xff820000 0x1000>;
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru MCLK_I2S2>, <&cru HCLK_I2S2>;
		clock-names = "i2s_clk", "i2s_hclk";
		dmas = <&dmac 24>, <&dmac 23>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2m0_sclk
			     &i2s2m0_lrck
			     &i2s2m0_sdi
			     &i2s2m0_sdo>;
		status = "disabled";
	};

	pdm: pdm@ff830000 {
		compatible = "rockchip,rv1126-pdm", "rockchip,pdm";
		reg = <0xff830000 0x1000>;
		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
		clock-names = "pdm_clk", "pdm_hclk";
		dmas = <&dmac 25>;
		dma-names = "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&pdmm0_clk
			     &pdmm0_clk1
			     &pdmm0_sdi0
			     &pdmm0_sdi1
			     &pdmm0_sdi2
			     &pdmm0_sdi3>;
		status = "disabled";
	};

	audpwm: audpwm@ff840000 {
		compatible = "rockchip,rv1126-audio-pwm", "rockchip,audio-pwm-v1";
		reg = <0xff840000 0x1000>;
		clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>;
		clock-names = "clk", "hclk";
		dmas = <&dmac 26>;
		dma-names = "tx";
		pinctrl-names = "default";
		pinctrl-0 = <&audpwmm0_pins>;
		rockchip,sample-width-bits = <11>;
		rockchip,interpolat-points = <1>;
		status = "disabled";
	};

	dfi: dfi@ff9c0000 {
		reg = <0xff9c0000 0x400>;
		compatible = "rockchip,rv1126-dfi";
		rockchip,pmugrf = <&pmugrf>;
		status = "disabled";
	};

	dmc: dmc {
		compatible = "rockchip,rv1126-dmc";
		devfreq-events = <&dfi>;
		clocks = <&cru SCLK_DDRCLK>;
		clock-names = "dmc_clk";
		operating-points-v2 = <&dmc_opp_table>;
		ddr_timing = <&ddr_timing>;
		upthreshold = <40>;
		downdifferential = <20>;
		system-status-freq = <
			/*system status         freq(KHz)*/
			SYS_STATUS_NORMAL       924000
			SYS_STATUS_REBOOT       450000
			SYS_STATUS_SUSPEND      328000
			SYS_STATUS_VIDEO_1080P  924000
			SYS_STATUS_BOOST        924000
			SYS_STATUS_ISP          924000
			SYS_STATUS_PERFORMANCE  924000
		>;
		auto-min-freq = <328000>;
		auto-freq-en = <0>;
		#cooling-cells = <2>;
		status = "disabled";
	};

	dmc_opp_table: dmc-opp-table {
		compatible = "operating-points-v2";

		opp-328000000 {
			opp-hz = /bits/ 64 <328000000>;
			opp-microvolt = <800000>;
		};
		opp-450000000 {
			opp-hz = /bits/ 64 <450000000>;
			opp-microvolt = <800000>;
		};
		opp-664000000 {
			opp-hz = /bits/ 64 <664000000>;
			opp-microvolt = <800000>;
		};
		opp-924000000 {
			opp-hz = /bits/ 64 <924000000>;
			opp-microvolt = <800000>;
		};
		opp-1056000000 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-microvolt = <800000>;
			status = "disabled";
		};
	};

	vop: vop@ffb00000 {
		compatible = "rockchip,rv1126-vop";
		reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
		reg-names = "regs", "gamma_lut";
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		iommus = <&vop_mmu>;
		status = "disabled";

		vop_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vop_out_rgb: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&rgb_in_vop>;
			};

			vop_out_dsi: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&dsi_in_vop>;
			};
		};
	};

	vop_mmu: iommu@ffb00f00 {
		compatible = "rockchip,iommu";
		reg = <0xffb00f00 0x100>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "vop_mmu";
		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		rockchip,disable-device-link-resume;
		status = "disabled";
	};

	dsi: dsi@ffb30000 {
		compatible = "rockchip,rv1126-mipi-dsi";
		reg = <0xffb30000 0x500>;
		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru PCLK_DSIHOST>, <&mipi_dphy>;
		clock-names = "pclk", "hs_clk";
		resets = <&cru SRST_DSIHOST_P>;
		reset-names = "apb";
		phys = <&mipi_dphy>;
		phy-names = "mipi_dphy";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ports {
			port {
				dsi_in_vop: endpoint {
					remote-endpoint = <&vop_out_dsi>;
				};
			};
		};
	};

	rkisp: rkisp@ffb50000 {
		compatible = "rockchip,rv1126-rkisp";
		reg = <0xffb50000 0x10000>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
			 <&cru CLK_ISP>;
		clock-names = "aclk_isp", "hclk_isp", "clk_isp";
		power-domains = <&power RV1126_PD_VI>;
		iommus = <&rkisp_mmu>;
		status = "disabled";
	};

	rkisp_mmu: iommu@ffb51a00 {
		compatible = "rockchip,iommu";
		reg = <0xffb51a00 0x100>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "isp_mmu";
		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
		clock-names = "aclk", "iface";
		power-domains = <&power RV1126_PD_VI>;
		#iommu-cells = <0>;
		rockchip,disable-mmu-reset;
		status = "disabled";
	};

	rkispp: rkispp@ffb60000 {
		compatible = "rockchip,rv1126-rkispp";
		reg = <0xffb60000 0x20000>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "ispp_irq", "fec_irq";
		clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>,
			 <&cru CLK_ISPP>;
		clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
		power-domains = <&power RV1126_PD_ISPP>;
		iommus = <&rkispp_mmu>;
		status = "disabled";
	};

	rkispp_mmu: iommu@ffb60e00 {
		compatible = "rockchip,iommu";
		reg = <0xffb60e00 0x40>, <0xffb60e40 0x40>, <0xffb60f00 0x40>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1";
		clocks = <&cru ACLK_ISPP>, <&cru HCLK_ISPP>;
		clock-names = "aclk", "iface";
		power-domains = <&power RV1126_PD_ISPP>;
		#iommu-cells = <0>;
		rockchip,disable-mmu-reset;
		status = "disabled";
	};

	rkvenc: rkvenc@ffbb0000 {
		compatible = "rockchip,rkv-encoder-v1";
		reg = <0xffbb0000 0x400>;
		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq_enc";
		clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>,
			<&cru CLK_VENC_CORE>;
		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
		resets = <&cru SRST_VENC_A>, <&cru SRST_VENC_H>,
			<&cru SRST_VENC_CORE>;
		reset-names = "video_a", "video_h", "video_core";
		iommus = <&rkvenc_mmu>;
		node-name = "rkvenc";
		rockchip,srv = <&mpp_srv>;
		rockchip,taskqueue-node = <2>;
		rockchip,resetgroup-node = <2>;
		power-domains = <&power RV1126_PD_VEPU>;
		status = "disabled";
	};

	rkvenc_mmu: iommu@ffbb0f00 {
		compatible = "rockchip,iommu";
		reg = <0xffbb0f00 0x40>, <0xffbb0f40 0x40>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1";
		clocks = <&cru ACLK_VENC>, <&cru HCLK_VENC>;
		clock-names = "aclk", "iface";
		rockchip,disable-mmu-reset;
		#iommu-cells = <0>;
		power-domains = <&power RV1126_PD_VEPU>;
		status = "disabled";
	};

	pvtm@ffc00000 {
		compatible = "rockchip,rv1126-npu-pvtm";
		reg = <0xffc00000 0x100>;
		clocks = <&cru CLK_NPUPVTM>, <&cru PCLK_NPUPVTM>;
		clock-names = "clk", "pclk";
		resets = <&cru SRST_NPUPVTM>, <&cru SRST_NPUPVTM_P>;
		reset-names = "clk", "pclk";
	};

	gmac: ethernet@ffc40000 {
		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
		reg = <0xffc40000 0x0ffff>;
		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq", "eth_wake_irq";
		rockchip,grf = <&grf>;
		clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
			 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
			 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
			 <&cru RGMII_MODE_CLK>, <&cru CLK_GMAC_PTPREF>;
		clock-names = "stmmaceth", "mac_clk_rx",
			      "mac_clk_tx", "clk_mac_refout",
			      "aclk_mac", "pclk_mac",
			      "clk_mac_speed", "ptp_ref";
		resets = <&cru SRST_GMAC_A>;
		reset-names = "stmmaceth";

		snps,mixed-burst;
		snps,tso;

		snps,axi-config = <&stmmac_axi_setup>;
		snps,mtl-rx-config = <&mtl_rx_setup>;
		snps,mtl-tx-config = <&mtl_tx_setup>;
		status = "disabled";

		mdio: mdio {
			compatible = "snps,dwmac-mdio";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		stmmac_axi_setup: stmmac-axi-config {
			snps,wr_osr_lmt = <4>;
			snps,rd_osr_lmt = <8>;
			snps,blen = <0 0 0 0 16 8 4>;
		};

		mtl_rx_setup: rx-queues-config {
			snps,rx-queues-to-use = <1>;
			queue0 {};
		};

		mtl_tx_setup: tx-queues-config {
			snps,tx-queues-to-use = <1>;
			queue0 {};
		};
	};

	emmc: dwmmc@ffc50000 {
		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0xffc50000 0x4000>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <200000000>;
		status = "disabled";
	};

	sdmmc: dwmmc@ffc60000 {
		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0xffc60000 0x4000>;
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <100000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_det &sdmmc1_bus4>;
		status = "disabled";
	};

	sdio: dwmmc@ffc70000 {
		compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0xffc70000 0x4000>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
		fifo-depth = <0x100>;
		max-frequency = <150000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>;
		status = "disabled";
	};

	nandc: nandc@ffc80000 {
		compatible = "rockchip,rk-nandc";
		reg = <0xffc80000 0x4000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		nandc_id = <0>;
		clocks = <&cru CLK_NANDC>, <&cru HCLK_NANDC>;
		clock-names = "clk_nandc", "hclk_nandc";
		status = "disabled";
	};

	sfc: sfc@ffc90000  {
		compatible = "rockchip,sfc";
		reg = <0xffc90000 0x4000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
		clock-names = "clk_sfc", "hclk_sfc";
		assigned-clocks = <&cru SCLK_SFC>;
		assigned-clock-rates = <80000000>;
		status = "disabled";
	};

	usbdrd: usb0 {
		compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		clocks = <&cru CLK_USBOTG_REF>, <&cru ACLK_USBOTG>;
		clock-names = "ref_clk", "bus_clk";
		status = "disabled";

		usbdrd_dwc3: dwc3@ffd00000 {
			compatible = "snps,dwc3";
			reg = <0xffd00000 0x100000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			dr_mode = "otg";
			maximum-speed = "high-speed";
			phys = <&u2phy_otg>;
			phy-names = "usb2-phy";
			phy_type = "utmi_wide";
			power-domains = <&power RV1126_PD_USB>;
			resets = <&cru SRST_USBOTG_A>;
			reset-names = "usb3-otg";
			snps,dis_enblslpm_quirk;
			snps,dis-u2-freeclk-exists-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis-del-phy-power-chg-quirk;
			snps,tx-ipgap-linecheck-dis-quirk;
			snps,xhci-trb-ent-quirk;
			status = "disabled";
		};
	};

	usb_host0_ehci: usb@ffe00000 {
		compatible = "generic-ehci";
		reg = <0xffe00000 0x20000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
			 <&u2phy1>;
		clock-names = "usbhost", "arbiter", "utmi";
		phys = <&u2phy_host>;
		phy-names = "usb";
		power-domains = <&power RV1126_PD_USB>;
		status = "disabled";
	};

	usb_host0_ohci: usb@ffe10000 {
		compatible = "generic-ohci";
		reg = <0xffe20000 0x20000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
			 <&u2phy1>;
		clock-names = "usbhost", "arbiter", "utmi";
		phys = <&u2phy_host>;
		phy-names = "usb";
		power-domains = <&power RV1126_PD_USB>;
		status = "disabled";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rv1126-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmugrf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@ff460000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff460000 0x100>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pmucru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@ff620000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff620000 0x100>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@ff630000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff630000 0x100>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@ff640000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff640000 0x100>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@ff650000 {
			compatible = "rockchip,gpio-bank";
			reg = <0xff650000 0x100>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};
};

#include "rv1126-pinctrl.dtsi"