1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 ethernet0 = &gmac0; 10 ethernet1 = &gmac1; 11 mmc0 = &sdhci; 12 mmc1 = &sdmmc0; 13 mmc2 = &sdmmc1; 14 }; 15 16 chosen { 17 stdout-path = &uart2; 18 u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor; 19 }; 20}; 21 22&crypto { 23 u-boot,dm-pre-reloc; 24}; 25 26&uart2 { 27 clock-frequency = <24000000>; 28 u-boot,dm-spl; 29 /delete-property/ pinctrl-names; 30 /delete-property/ pinctrl-0; 31 status = "okay"; 32}; 33 34&grf { 35 u-boot,dm-pre-reloc; 36 status = "okay"; 37}; 38 39&pmugrf { 40 u-boot,dm-pre-reloc; 41 status = "okay"; 42}; 43 44&usb2phy0_grf { 45 u-boot,dm-pre-reloc; 46 status = "okay"; 47}; 48 49&usbdrd30 { 50 u-boot,dm-pre-reloc; 51 status = "okay"; 52}; 53 54&usbdrd_dwc3 { 55 u-boot,dm-pre-reloc; 56 status = "okay"; 57}; 58 59&usbhost30 { 60 u-boot,dm-pre-reloc; 61 status = "okay"; 62}; 63 64&usbhost_dwc3 { 65 u-boot,dm-pre-reloc; 66 status = "okay"; 67}; 68 69&usb2phy0 { 70 u-boot,dm-pre-reloc; 71 status = "okay"; 72}; 73 74&u2phy0_otg { 75 u-boot,dm-pre-reloc; 76 status = "okay"; 77}; 78 79&u2phy0_host { 80 u-boot,dm-pre-reloc; 81 status = "okay"; 82}; 83 84&cru { 85 u-boot,dm-pre-reloc; 86 status = "okay"; 87}; 88 89&pmucru { 90 u-boot,dm-pre-reloc; 91 status = "okay"; 92}; 93 94&sfc { 95 u-boot,dm-spl; 96 /delete-property/ pinctrl-names; 97 /delete-property/ pinctrl-0; 98 /delete-property/ assigned-clocks; 99 /delete-property/ assigned-clock-rates; 100 status = "okay"; 101 102 #address-cells = <1>; 103 #size-cells = <0>; 104 spi_nand: flash@0 { 105 u-boot,dm-spl; 106 compatible = "spi-nand"; 107 reg = <0>; 108 spi-tx-bus-width = <1>; 109 spi-rx-bus-width = <4>; 110 spi-max-frequency = <96000000>; 111 }; 112 113 spi_nor: flash@1 { 114 u-boot,dm-spl; 115 compatible = "jedec,spi-nor"; 116 label = "sfc_nor"; 117 reg = <0>; 118 spi-tx-bus-width = <1>; 119 spi-rx-bus-width = <4>; 120 spi-max-frequency = <100000000>; 121 }; 122}; 123 124&saradc { 125 u-boot,dm-spl; 126 status = "okay"; 127}; 128 129&sdmmc0 { 130 u-boot,dm-spl; 131 status = "okay"; 132}; 133 134&sdmmc0_pins { 135 u-boot,dm-spl; 136}; 137 138&sdmmc0_bus4 { 139 u-boot,dm-spl; 140}; 141 142&sdmmc0_clk { 143 u-boot,dm-spl; 144}; 145 146&sdmmc0_cmd { 147 u-boot,dm-spl; 148}; 149 150&sdmmc0_det { 151 u-boot,dm-spl; 152}; 153 154&sdmmc1 { 155 u-boot,dm-spl; 156 /delete-property/ pinctrl-names; 157 /delete-property/ pinctrl-0; 158 status = "okay"; 159}; 160 161&sdhci { 162 bus-width = <8>; 163 u-boot,dm-spl; 164 /delete-property/ pinctrl-names; 165 /delete-property/ pinctrl-0; 166 mmc-hs200-1_8v; 167 status = "okay"; 168}; 169 170&nandc0 { 171 u-boot,dm-spl; 172 status = "okay"; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 /delete-property/ pinctrl-names; 176 /delete-property/ pinctrl-0; 177 178 nand@0 { 179 u-boot,dm-spl; 180 reg = <0>; 181 nand-ecc-mode = "hw_syndrome"; 182 nand-ecc-strength = <16>; 183 nand-ecc-step-size = <1024>; 184 }; 185}; 186 187 188&gmac0_clkin{ 189 u-boot,dm-pre-reloc; 190}; 191 192&gmac1_clkin { 193 u-boot,dm-pre-reloc; 194}; 195 196&gmac0 { 197 u-boot,dm-pre-reloc; 198 phy-mode = "rgmii"; 199 clock_in_out = "output"; 200 201 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 202 snps,reset-active-low; 203 /* Reset time is 20ms, 100ms for rtl8211f */ 204 snps,reset-delays-us = <0 20000 100000>; 205 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 206 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 207 assigned-clock-rates = <0>, <125000000>; 208 209 pinctrl-names = "default"; 210 pinctrl-0 = <&gmac0_miim 211 &gmac0_tx_bus2 212 &gmac0_rx_bus2 213 &gmac0_rgmii_clk 214 &gmac0_rgmii_bus>; 215 216 tx_delay = <0x3c>; 217 rx_delay = <0x2f>; 218 219 phy-handle = <&rgmii_phy0>; 220 status = "disabled"; 221}; 222 223&gmac1 { 224 u-boot,dm-pre-reloc; 225 phy-mode = "rgmii"; 226 clock_in_out = "output"; 227 228 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 229 snps,reset-active-low; 230 /* Reset time is 20ms, 100ms for rtl8211f */ 231 snps,reset-delays-us = <0 20000 100000>; 232 233 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 234 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 235 assigned-clock-rates = <0>, <125000000>; 236 237 pinctrl-names = "default"; 238 pinctrl-0 = <&gmac1m1_miim 239 &gmac1m1_tx_bus2 240 &gmac1m1_rx_bus2 241 &gmac1m1_rgmii_clk 242 &gmac1m1_rgmii_bus>; 243 244 tx_delay = <0x4f>; 245 rx_delay = <0x26>; 246 247 phy-handle = <&rgmii_phy1>; 248 status = "disabled"; 249}; 250 251&gmac0_stmmac_axi_setup { 252 u-boot,dm-pre-reloc; 253}; 254 255&gmac0_mtl_rx_setup { 256 u-boot,dm-pre-reloc; 257 queue0 { 258 u-boot,dm-pre-reloc; 259 }; 260}; 261 262&gmac0_mtl_tx_setup { 263 u-boot,dm-pre-reloc; 264 queue0 { 265 u-boot,dm-pre-reloc; 266 }; 267}; 268 269&gmac1_stmmac_axi_setup { 270 u-boot,dm-pre-reloc; 271}; 272 273&gmac1_mtl_rx_setup { 274 u-boot,dm-pre-reloc; 275 queue0 { 276 u-boot,dm-pre-reloc; 277 }; 278}; 279 280&gmac1_mtl_tx_setup { 281 u-boot,dm-pre-reloc; 282 queue0 { 283 u-boot,dm-pre-reloc; 284 }; 285}; 286 287&mdio0 { 288 u-boot,dm-pre-reloc; 289 rgmii_phy0: phy@0 { 290 compatible = "ethernet-phy-ieee802.3-c22"; 291 u-boot,dm-pre-reloc; 292 reg = <0x0>; 293 }; 294}; 295 296&mdio1 { 297 u-boot,dm-pre-reloc; 298 rgmii_phy1: phy@0 { 299 compatible = "ethernet-phy-ieee802.3-c22"; 300 u-boot,dm-pre-reloc; 301 reg = <0x0>; 302 }; 303}; 304 305&gmac0_miim { 306 u-boot,dm-pre-reloc; 307}; 308 309&gmac0_clkinout { 310 u-boot,dm-pre-reloc; 311}; 312 313&gmac0_rx_bus2 { 314 u-boot,dm-pre-reloc; 315}; 316 317&gmac0_tx_bus2 { 318 u-boot,dm-pre-reloc; 319}; 320 321&gmac0_rgmii_clk { 322 u-boot,dm-pre-reloc; 323}; 324 325&gmac0_rgmii_bus { 326 u-boot,dm-pre-reloc; 327}; 328 329&gmac1m1_miim { 330 u-boot,dm-pre-reloc; 331}; 332 333&gmac1m1_clkinout { 334 u-boot,dm-pre-reloc; 335}; 336 337&gmac1m1_rx_bus2 { 338 u-boot,dm-pre-reloc; 339}; 340 341&gmac1m1_tx_bus2 { 342 u-boot,dm-pre-reloc; 343}; 344 345&gmac1m1_rgmii_clk { 346 u-boot,dm-pre-reloc; 347}; 348 349&gmac1m1_rgmii_bus { 350 u-boot,dm-pre-reloc; 351}; 352 353ð0_clkout_pins { 354 u-boot,dm-pre-reloc; 355}; 356 357ð1m1_clkout_pins { 358 u-boot,dm-pre-reloc; 359}; 360 361&pinctrl { 362 u-boot,dm-pre-reloc; 363 status = "okay"; 364}; 365 366&gpio0 { 367 u-boot,dm-spl; 368}; 369 370&gpio1 { 371 u-boot,dm-spl; 372}; 373 374&gpio2 { 375 u-boot,dm-pre-reloc; 376}; 377 378&pcfg_pull_none_drv_level_1 { 379 u-boot,dm-pre-reloc; 380}; 381 382&pcfg_pull_none_drv_level_2 { 383 u-boot,dm-pre-reloc; 384}; 385 386 387&pcfg_pull_up_drv_level_1 { 388 u-boot,dm-spl; 389}; 390 391&pcfg_pull_up_drv_level_2 { 392 u-boot,dm-spl; 393}; 394 395&pcfg_pull_none { 396 u-boot,dm-pre-reloc; 397}; 398 399&secure_otp { 400 u-boot,dm-spl; 401}; 402 403&wdt { 404 u-boot,dm-pre-reloc; 405 status = "okay"; 406}; 407