xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3568-u-boot.dtsi (revision e091b6c996a68a6a0faa2bd3ffdd90b3ba5f44ce) 
1/*
2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		ethernet0 = &gmac0;
10		ethernet1 = &gmac1;
11		mmc0 = &sdhci;
12		mmc1 = &sdmmc0;
13		mmc2 = &sdmmc1;
14	};
15
16	chosen {
17		stdout-path = &uart2;
18		u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
19	};
20};
21
22&crypto {
23	u-boot,dm-pre-reloc;
24};
25
26&uart2 {
27	clock-frequency = <24000000>;
28	u-boot,dm-spl;
29	/delete-property/ pinctrl-names;
30	/delete-property/ pinctrl-0;
31	status = "okay";
32};
33
34&grf {
35	u-boot,dm-pre-reloc;
36	status = "okay";
37};
38
39&pmugrf {
40	u-boot,dm-pre-reloc;
41	status = "okay";
42};
43
44&usb2phy0_grf {
45	u-boot,dm-pre-reloc;
46	status = "okay";
47};
48
49&usbdrd30 {
50	u-boot,dm-pre-reloc;
51	status = "okay";
52};
53
54&usbdrd_dwc3 {
55	u-boot,dm-pre-reloc;
56	status = "okay";
57};
58
59&usbhost30 {
60	u-boot,dm-pre-reloc;
61	status = "okay";
62};
63
64&usbhost_dwc3 {
65	u-boot,dm-pre-reloc;
66	status = "okay";
67};
68
69&usb2phy0 {
70	u-boot,dm-pre-reloc;
71	status = "okay";
72};
73
74&u2phy0_otg {
75	u-boot,dm-pre-reloc;
76	status = "okay";
77};
78
79&u2phy0_host {
80	u-boot,dm-pre-reloc;
81	status = "okay";
82};
83
84&cru {
85	u-boot,dm-pre-reloc;
86	status = "okay";
87};
88
89&pmucru {
90	u-boot,dm-pre-reloc;
91	status = "okay";
92};
93
94&rng {
95	u-boot,dm-pre-reloc;
96	status = "okay";
97};
98
99&sfc {
100	u-boot,dm-spl;
101	/delete-property/ pinctrl-names;
102	/delete-property/ pinctrl-0;
103	/delete-property/ assigned-clocks;
104	/delete-property/ assigned-clock-rates;
105	status = "okay";
106
107	#address-cells = <1>;
108	#size-cells = <0>;
109	spi_nand: flash@0 {
110		u-boot,dm-spl;
111		compatible = "spi-nand";
112		reg = <0>;
113		spi-tx-bus-width = <1>;
114		spi-rx-bus-width = <4>;
115		spi-max-frequency = <96000000>;
116	};
117
118	spi_nor: flash@1 {
119		u-boot,dm-spl;
120		compatible = "jedec,spi-nor";
121		label = "sfc_nor";
122		reg = <0>;
123		spi-tx-bus-width = <1>;
124		spi-rx-bus-width = <4>;
125		spi-max-frequency = <100000000>;
126	};
127};
128
129&saradc {
130	u-boot,dm-spl;
131	status = "okay";
132};
133
134&sdmmc0 {
135	u-boot,dm-spl;
136	status = "okay";
137};
138
139&sdmmc0_pins {
140	u-boot,dm-spl;
141};
142
143&sdmmc0_bus4 {
144	u-boot,dm-spl;
145};
146
147&sdmmc0_clk {
148	u-boot,dm-spl;
149};
150
151&sdmmc0_cmd {
152	u-boot,dm-spl;
153};
154
155&sdmmc0_det {
156	u-boot,dm-spl;
157};
158
159&sdmmc1 {
160	u-boot,dm-spl;
161	/delete-property/ pinctrl-names;
162	/delete-property/ pinctrl-0;
163	status = "okay";
164};
165
166&sdhci {
167	bus-width = <8>;
168	u-boot,dm-spl;
169	/delete-property/ pinctrl-names;
170	/delete-property/ pinctrl-0;
171	mmc-hs200-1_8v;
172	status = "okay";
173};
174
175&nandc0 {
176	u-boot,dm-spl;
177	status = "okay";
178	#address-cells = <1>;
179	#size-cells = <0>;
180	/delete-property/ pinctrl-names;
181	/delete-property/ pinctrl-0;
182
183	nand@0 {
184		u-boot,dm-spl;
185		reg = <0>;
186		nand-ecc-mode = "hw_syndrome";
187		nand-ecc-strength = <16>;
188		nand-ecc-step-size = <1024>;
189	};
190};
191
192&gmac0_clkin{
193	u-boot,dm-pre-reloc;
194};
195
196&gmac1_clkin {
197	u-boot,dm-pre-reloc;
198};
199
200&gmac0 {
201	u-boot,dm-pre-reloc;
202	phy-mode = "rgmii";
203	clock_in_out = "output";
204
205	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
206	snps,reset-active-low;
207	/* Reset time is 20ms, 100ms for rtl8211f */
208	snps,reset-delays-us = <0 20000 100000>;
209	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
210	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
211	assigned-clock-rates = <0>, <125000000>;
212
213	pinctrl-names = "default";
214	pinctrl-0 = <&gmac0_miim
215		     &gmac0_tx_bus2
216		     &gmac0_rx_bus2
217		     &gmac0_rgmii_clk
218		     &gmac0_rgmii_bus>;
219
220	tx_delay = <0x3c>;
221	rx_delay = <0x2f>;
222
223	phy-handle = <&rgmii_phy0>;
224	status = "disabled";
225};
226
227&gmac1 {
228	u-boot,dm-pre-reloc;
229	phy-mode = "rgmii";
230	clock_in_out = "output";
231
232	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
233	snps,reset-active-low;
234	/* Reset time is 20ms, 100ms for rtl8211f */
235	snps,reset-delays-us = <0 20000 100000>;
236
237	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
238	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
239	assigned-clock-rates = <0>, <125000000>;
240
241	pinctrl-names = "default";
242	pinctrl-0 = <&gmac1m1_miim
243		     &gmac1m1_tx_bus2
244		     &gmac1m1_rx_bus2
245		     &gmac1m1_rgmii_clk
246		     &gmac1m1_rgmii_bus>;
247
248	tx_delay = <0x4f>;
249	rx_delay = <0x26>;
250
251	phy-handle = <&rgmii_phy1>;
252	status = "disabled";
253};
254
255&gmac0_stmmac_axi_setup {
256	u-boot,dm-pre-reloc;
257};
258
259&gmac0_mtl_rx_setup {
260	u-boot,dm-pre-reloc;
261	queue0 {
262		u-boot,dm-pre-reloc;
263	};
264};
265
266&gmac0_mtl_tx_setup {
267	u-boot,dm-pre-reloc;
268	queue0 {
269		u-boot,dm-pre-reloc;
270	};
271};
272
273&gmac1_stmmac_axi_setup {
274	u-boot,dm-pre-reloc;
275};
276
277&gmac1_mtl_rx_setup {
278	u-boot,dm-pre-reloc;
279	queue0 {
280		u-boot,dm-pre-reloc;
281	};
282};
283
284&gmac1_mtl_tx_setup {
285	u-boot,dm-pre-reloc;
286	queue0 {
287		u-boot,dm-pre-reloc;
288	};
289};
290
291&mdio0 {
292	u-boot,dm-pre-reloc;
293	rgmii_phy0: phy@0 {
294		compatible = "ethernet-phy-ieee802.3-c22";
295		u-boot,dm-pre-reloc;
296		reg = <0x0>;
297	};
298};
299
300&mdio1 {
301	u-boot,dm-pre-reloc;
302	rgmii_phy1: phy@0 {
303		compatible = "ethernet-phy-ieee802.3-c22";
304		u-boot,dm-pre-reloc;
305		reg = <0x0>;
306	};
307};
308
309&gmac0_miim {
310	u-boot,dm-pre-reloc;
311};
312
313&gmac0_clkinout {
314	u-boot,dm-pre-reloc;
315};
316
317&gmac0_rx_bus2 {
318	u-boot,dm-pre-reloc;
319};
320
321&gmac0_tx_bus2 {
322	u-boot,dm-pre-reloc;
323};
324
325&gmac0_rgmii_clk {
326	u-boot,dm-pre-reloc;
327};
328
329&gmac0_rgmii_bus {
330	u-boot,dm-pre-reloc;
331};
332
333&gmac1m1_miim {
334	u-boot,dm-pre-reloc;
335};
336
337&gmac1m1_clkinout {
338	u-boot,dm-pre-reloc;
339};
340
341&gmac1m1_rx_bus2 {
342	u-boot,dm-pre-reloc;
343};
344
345&gmac1m1_tx_bus2 {
346	u-boot,dm-pre-reloc;
347};
348
349&gmac1m1_rgmii_clk {
350	u-boot,dm-pre-reloc;
351};
352
353&gmac1m1_rgmii_bus {
354	u-boot,dm-pre-reloc;
355};
356
357&eth0_clkout_pins {
358	u-boot,dm-pre-reloc;
359};
360
361&eth1m1_clkout_pins {
362	u-boot,dm-pre-reloc;
363};
364
365&pcie30phy {
366	u-boot,dm-pre-reloc;
367	status = "okay";
368};
369
370&pcie3x2 {
371	u-boot,dm-pre-reloc;
372	status = "okay";
373};
374
375&pinctrl {
376	u-boot,dm-pre-reloc;
377	status = "okay";
378};
379
380&gpio0 {
381	u-boot,dm-spl;
382};
383
384&gpio1 {
385	u-boot,dm-spl;
386};
387
388&gpio2 {
389	u-boot,dm-pre-reloc;
390};
391
392&pcfg_pull_none_drv_level_1 {
393	u-boot,dm-pre-reloc;
394};
395
396&pcfg_pull_none_drv_level_2 {
397	u-boot,dm-pre-reloc;
398};
399
400
401&pcfg_pull_up_drv_level_1 {
402	u-boot,dm-spl;
403};
404
405&pcfg_pull_up_drv_level_2 {
406	u-boot,dm-spl;
407};
408
409&pcfg_pull_up {
410	u-boot,dm-spl;
411};
412
413&pcfg_pull_none {
414	u-boot,dm-pre-reloc;
415};
416
417&secure_otp {
418	u-boot,dm-spl;
419};
420
421&wdt {
422	u-boot,dm-pre-reloc;
423	status = "okay";
424};
425