1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &sdhci; 10 mmc1 = &sdmmc0; 11 mmc2 = &sdmmc1; 12 }; 13 14 chosen { 15 stdout-path = &uart2; 16 }; 17}; 18 19&uart2 { 20 clock-frequency = <24000000>; 21 u-boot,dm-pre-reloc; 22 status = "okay"; 23}; 24 25&grf { 26 u-boot,dm-pre-reloc; 27 status = "okay"; 28}; 29 30&pmugrf { 31 u-boot,dm-pre-reloc; 32 status = "okay"; 33}; 34 35&cru { 36 u-boot,dm-pre-reloc; 37 status = "okay"; 38}; 39 40&pmucru { 41 u-boot,dm-pre-reloc; 42 status = "okay"; 43}; 44 45&sfc { 46 u-boot,dm-spl; 47 /delete-property/ assigned-clocks; 48 /delete-property/ assigned-clock-rates; 49 status = "okay"; 50 51 #address-cells = <1>; 52 #size-cells = <0>; 53 spi_nand: flash@0 { 54 u-boot,dm-spl; 55 compatible = "spi-nand"; 56 reg = <0>; 57 spi-tx-bus-width = <1>; 58 spi-rx-bus-width = <4>; 59 spi-max-frequency = <96000000>; 60 }; 61 62 spi_nor: flash@1 { 63 u-boot,dm-spl; 64 compatible = "jedec,spi-nor"; 65 label = "sfc_nor"; 66 reg = <0>; 67 spi-tx-bus-width = <1>; 68 spi-rx-bus-width = <4>; 69 spi-max-frequency = <100000000>; 70 }; 71}; 72 73&saradc { 74 u-boot,dm-spl; 75 status = "okay"; 76}; 77 78&sdmmc0 { 79 u-boot,dm-pre-reloc; 80 status = "okay"; 81}; 82 83&sdmmc1 { 84 u-boot,dm-pre-reloc; 85 status = "okay"; 86}; 87 88&sdhci { 89 u-boot,dm-pre-reloc; 90 status = "okay"; 91}; 92 93