xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3568-u-boot.dtsi (revision a8a4d6c05a2e5f52e75e5096f9470aa3d36fd000) 
1/*
2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		ethernet0 = &gmac0;
10		ethernet1 = &gmac1;
11		mmc0 = &sdhci;
12		mmc1 = &sdmmc0;
13		mmc2 = &sdmmc1;
14	};
15
16	chosen {
17		stdout-path = &uart2;
18		u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
19	};
20
21	secure-otp@fe3a0000 {
22		compatible = "rockchip,rk3568-secure-otp";
23		reg = <0x0 0xfe3a0000 0x0 0x4000>;
24		secure_conf = <0xfdd18008>;
25		mask_addr = <0xfe880000>;
26		cru_rst_addr = <0xfdd20470>;
27		u-boot,dm-spl;
28	};
29};
30
31&psci {
32	u-boot,dm-pre-reloc;
33	status = "okay";
34};
35
36&combphy0_us {
37	u-boot,dm-pre-reloc;
38	status = "okay";
39};
40
41&crypto {
42	u-boot,dm-spl;
43};
44
45&uart2 {
46	clock-frequency = <24000000>;
47	u-boot,dm-spl;
48	/delete-property/ pinctrl-names;
49	/delete-property/ pinctrl-0;
50	status = "okay";
51};
52
53&grf {
54	u-boot,dm-spl;
55	status = "okay";
56};
57
58&pipegrf {
59	u-boot,dm-pre-reloc;
60};
61
62&pipe_phy_grf0 {
63	u-boot,dm-pre-reloc;
64};
65
66&pmugrf {
67	u-boot,dm-spl;
68	status = "okay";
69};
70
71&usb2phy0_grf {
72	u-boot,dm-pre-reloc;
73	status = "okay";
74};
75
76&usb2phy0 {
77	u-boot,dm-pre-reloc;
78	status = "okay";
79};
80
81&u2phy0_otg {
82	u-boot,dm-pre-reloc;
83	status = "okay";
84};
85
86&u2phy0_host {
87	u-boot,dm-pre-reloc;
88	status = "okay";
89};
90
91&cru {
92	u-boot,dm-spl;
93	status = "okay";
94};
95
96&pmucru {
97	u-boot,dm-spl;
98	status = "okay";
99};
100
101&rng {
102	u-boot,dm-pre-reloc;
103	status = "okay";
104};
105
106&sfc {
107	u-boot,dm-spl;
108	/delete-property/ pinctrl-names;
109	/delete-property/ pinctrl-0;
110	/delete-property/ assigned-clocks;
111	/delete-property/ assigned-clock-rates;
112	status = "okay";
113
114	#address-cells = <1>;
115	#size-cells = <0>;
116	spi_nand: flash@0 {
117		u-boot,dm-spl;
118		compatible = "spi-nand";
119		reg = <0>;
120		spi-tx-bus-width = <1>;
121		spi-rx-bus-width = <4>;
122		spi-max-frequency = <75000000>;
123	};
124
125	spi_nor: flash@1 {
126		u-boot,dm-spl;
127		compatible = "jedec,spi-nor";
128		label = "sfc_nor";
129		reg = <0>;
130		spi-tx-bus-width = <1>;
131		spi-rx-bus-width = <4>;
132		spi-max-frequency = <100000000>;
133	};
134};
135
136&saradc {
137	u-boot,dm-pre-reloc;
138	status = "okay";
139};
140
141&sdmmc0 {
142	u-boot,dm-spl;
143	status = "okay";
144};
145
146&sdmmc0_pins {
147	u-boot,dm-spl;
148};
149
150&sdmmc0_bus4 {
151	u-boot,dm-spl;
152};
153
154&sdmmc0_clk {
155	u-boot,dm-spl;
156};
157
158&sdmmc0_cmd {
159	u-boot,dm-spl;
160};
161
162&sdmmc0_det {
163	u-boot,dm-spl;
164};
165
166&sdmmc1 {
167	u-boot,dm-spl;
168	/delete-property/ pinctrl-names;
169	/delete-property/ pinctrl-0;
170	status = "okay";
171};
172
173&sdhci {
174	bus-width = <8>;
175	u-boot,dm-spl;
176	/delete-property/ pinctrl-names;
177	/delete-property/ pinctrl-0;
178	mmc-hs200-1_8v;
179	status = "okay";
180};
181
182&nandc0 {
183	u-boot,dm-spl;
184	status = "okay";
185	#address-cells = <1>;
186	#size-cells = <0>;
187	/delete-property/ pinctrl-names;
188	/delete-property/ pinctrl-0;
189
190	nand@0 {
191		u-boot,dm-spl;
192		reg = <0>;
193		nand-ecc-mode = "hw";
194		nand-ecc-strength = <16>;
195		nand-ecc-step-size = <1024>;
196	};
197};
198
199&gmac0_clkin {
200	u-boot,dm-pre-reloc;
201};
202
203&gmac1_clkin {
204	u-boot,dm-pre-reloc;
205};
206
207&gmac0 {
208	u-boot,dm-pre-reloc;
209	phy-mode = "rgmii";
210	clock_in_out = "output";
211
212	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
213	snps,reset-active-low;
214	/* Reset time is 20ms, 100ms for rtl8211f */
215	snps,reset-delays-us = <0 20000 100000>;
216	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
217	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
218	assigned-clock-rates = <0>, <125000000>;
219
220	pinctrl-names = "default";
221	pinctrl-0 = <&gmac0_miim
222		     &gmac0_tx_bus2
223		     &gmac0_rx_bus2
224		     &gmac0_rgmii_clk
225		     &gmac0_rgmii_bus>;
226
227	tx_delay = <0x3c>;
228	rx_delay = <0x2f>;
229
230	phy-handle = <&rgmii_phy0>;
231	status = "disabled";
232};
233
234&gmac1 {
235	u-boot,dm-pre-reloc;
236	phy-mode = "rgmii";
237	clock_in_out = "output";
238
239	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
240	snps,reset-active-low;
241	/* Reset time is 20ms, 100ms for rtl8211f */
242	snps,reset-delays-us = <0 20000 100000>;
243
244	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
245	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
246	assigned-clock-rates = <0>, <125000000>;
247
248	pinctrl-names = "default";
249	pinctrl-0 = <&gmac1m1_miim
250		     &gmac1m1_tx_bus2
251		     &gmac1m1_rx_bus2
252		     &gmac1m1_rgmii_clk
253		     &gmac1m1_rgmii_bus>;
254
255	tx_delay = <0x4f>;
256	rx_delay = <0x26>;
257
258	phy-handle = <&rgmii_phy1>;
259	status = "disabled";
260};
261
262&gmac0_stmmac_axi_setup {
263	u-boot,dm-pre-reloc;
264};
265
266&gmac0_mtl_rx_setup {
267	u-boot,dm-pre-reloc;
268	queue0 {
269		u-boot,dm-pre-reloc;
270	};
271};
272
273&gmac0_mtl_tx_setup {
274	u-boot,dm-pre-reloc;
275	queue0 {
276		u-boot,dm-pre-reloc;
277	};
278};
279
280&gmac1_stmmac_axi_setup {
281	u-boot,dm-pre-reloc;
282};
283
284&gmac1_mtl_rx_setup {
285	u-boot,dm-pre-reloc;
286	queue0 {
287		u-boot,dm-pre-reloc;
288	};
289};
290
291&gmac1_mtl_tx_setup {
292	u-boot,dm-pre-reloc;
293	queue0 {
294		u-boot,dm-pre-reloc;
295	};
296};
297
298&mdio0 {
299	u-boot,dm-pre-reloc;
300	rgmii_phy0: phy@0 {
301		compatible = "ethernet-phy-ieee802.3-c22";
302		u-boot,dm-pre-reloc;
303		reg = <0x0>;
304	};
305};
306
307&mdio1 {
308	u-boot,dm-pre-reloc;
309	rgmii_phy1: phy@0 {
310		compatible = "ethernet-phy-ieee802.3-c22";
311		u-boot,dm-pre-reloc;
312		reg = <0x0>;
313	};
314};
315
316&gmac0_miim {
317	u-boot,dm-pre-reloc;
318};
319
320&gmac0_clkinout {
321	u-boot,dm-pre-reloc;
322};
323
324&gmac0_rx_bus2 {
325	u-boot,dm-pre-reloc;
326};
327
328&gmac0_tx_bus2 {
329	u-boot,dm-pre-reloc;
330};
331
332&gmac0_rgmii_clk {
333	u-boot,dm-pre-reloc;
334};
335
336&gmac0_rgmii_bus {
337	u-boot,dm-pre-reloc;
338};
339
340&gmac1m1_miim {
341	u-boot,dm-pre-reloc;
342};
343
344&gmac1m1_clkinout {
345	u-boot,dm-pre-reloc;
346};
347
348&gmac1m1_rx_bus2 {
349	u-boot,dm-pre-reloc;
350};
351
352&gmac1m1_tx_bus2 {
353	u-boot,dm-pre-reloc;
354};
355
356&gmac1m1_rgmii_clk {
357	u-boot,dm-pre-reloc;
358};
359
360&gmac1m1_rgmii_bus {
361	u-boot,dm-pre-reloc;
362};
363
364&eth0_clkout_pins {
365	u-boot,dm-pre-reloc;
366};
367
368&eth1m1_clkout_pins {
369	u-boot,dm-pre-reloc;
370};
371
372&pcie30phy {
373	u-boot,dm-pre-reloc;
374	status = "okay";
375};
376
377&pcie3x2 {
378	u-boot,dm-pre-reloc;
379	status = "okay";
380};
381
382&pinctrl {
383	u-boot,dm-spl;
384	status = "okay";
385};
386
387&gpio0 {
388	u-boot,dm-spl;
389};
390
391&gpio1 {
392	u-boot,dm-spl;
393};
394
395&gpio2 {
396	u-boot,dm-spl;
397};
398
399&pcfg_pull_none_drv_level_1 {
400	u-boot,dm-spl;
401};
402
403&pcfg_pull_none_drv_level_2 {
404	u-boot,dm-spl;
405};
406
407
408&pcfg_pull_up_drv_level_1 {
409	u-boot,dm-spl;
410};
411
412&pcfg_pull_up_drv_level_2 {
413	u-boot,dm-spl;
414};
415
416&pcfg_pull_up {
417	u-boot,dm-spl;
418};
419
420&pcfg_pull_none {
421	u-boot,dm-spl;
422};
423
424&wdt {
425	u-boot,dm-pre-reloc;
426	status = "okay";
427};
428
429#if 0
430&i2c0 {
431	u-boot,dm-pre-reloc;
432	status = "okay";
433};
434
435&i2c0_xfer {
436	u-boot,dm-pre-reloc;
437	status = "okay";
438};
439
440&i2c1 {
441	u-boot,dm-pre-reloc;
442	status = "okay";
443};
444
445&i2c1_xfer {
446	u-boot,dm-pre-reloc;
447	status = "okay";
448};
449
450&pcfg_pull_none_smt {
451	u-boot,dm-pre-reloc;
452	status = "okay";
453};
454#endif
455
456