xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3568-u-boot.dtsi (revision 7a00f0a44b0ec80f61ab1cd47fc45a04869bbfa3) 
1/*
2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		ethernet0 = &gmac0;
10		ethernet1 = &gmac1;
11		mmc0 = &sdhci;
12		mmc1 = &sdmmc0;
13		mmc2 = &sdmmc1;
14	};
15
16	chosen {
17		stdout-path = &uart2;
18		u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
19	};
20};
21
22&psci {
23	u-boot,dm-pre-reloc;
24	status = "okay";
25};
26
27&crypto {
28	u-boot,dm-pre-reloc;
29};
30
31&uart2 {
32	clock-frequency = <24000000>;
33	u-boot,dm-spl;
34	/delete-property/ pinctrl-names;
35	/delete-property/ pinctrl-0;
36	status = "okay";
37};
38
39&grf {
40	u-boot,dm-pre-reloc;
41	status = "okay";
42};
43
44&pmugrf {
45	u-boot,dm-pre-reloc;
46	status = "okay";
47};
48
49&usb2phy0_grf {
50	u-boot,dm-pre-reloc;
51	status = "okay";
52};
53
54&usbdrd30 {
55	u-boot,dm-pre-reloc;
56	status = "okay";
57};
58
59&usbdrd_dwc3 {
60	u-boot,dm-pre-reloc;
61	status = "okay";
62};
63
64&usbhost30 {
65	u-boot,dm-pre-reloc;
66	status = "okay";
67};
68
69&usbhost_dwc3 {
70	u-boot,dm-pre-reloc;
71	status = "okay";
72};
73
74&usb2phy0 {
75	u-boot,dm-pre-reloc;
76	status = "okay";
77};
78
79&u2phy0_otg {
80	u-boot,dm-pre-reloc;
81	status = "okay";
82};
83
84&u2phy0_host {
85	u-boot,dm-pre-reloc;
86	status = "okay";
87};
88
89&cru {
90	u-boot,dm-pre-reloc;
91	status = "okay";
92};
93
94&pmucru {
95	u-boot,dm-pre-reloc;
96	status = "okay";
97};
98
99&rng {
100	u-boot,dm-pre-reloc;
101	status = "okay";
102};
103
104&sfc {
105	u-boot,dm-spl;
106	/delete-property/ pinctrl-names;
107	/delete-property/ pinctrl-0;
108	/delete-property/ assigned-clocks;
109	/delete-property/ assigned-clock-rates;
110	status = "okay";
111
112	#address-cells = <1>;
113	#size-cells = <0>;
114	spi_nand: flash@0 {
115		u-boot,dm-spl;
116		compatible = "spi-nand";
117		reg = <0>;
118		spi-tx-bus-width = <1>;
119		spi-rx-bus-width = <4>;
120		spi-max-frequency = <96000000>;
121	};
122
123	spi_nor: flash@1 {
124		u-boot,dm-spl;
125		compatible = "jedec,spi-nor";
126		label = "sfc_nor";
127		reg = <0>;
128		spi-tx-bus-width = <1>;
129		spi-rx-bus-width = <4>;
130		spi-max-frequency = <100000000>;
131	};
132};
133
134&saradc {
135	u-boot,dm-spl;
136	status = "okay";
137};
138
139&sdmmc0 {
140	u-boot,dm-spl;
141	status = "okay";
142};
143
144&sdmmc0_pins {
145	u-boot,dm-spl;
146};
147
148&sdmmc0_bus4 {
149	u-boot,dm-spl;
150};
151
152&sdmmc0_clk {
153	u-boot,dm-spl;
154};
155
156&sdmmc0_cmd {
157	u-boot,dm-spl;
158};
159
160&sdmmc0_det {
161	u-boot,dm-spl;
162};
163
164&sdmmc1 {
165	u-boot,dm-spl;
166	/delete-property/ pinctrl-names;
167	/delete-property/ pinctrl-0;
168	status = "okay";
169};
170
171&sdhci {
172	bus-width = <8>;
173	u-boot,dm-spl;
174	/delete-property/ pinctrl-names;
175	/delete-property/ pinctrl-0;
176	mmc-hs200-1_8v;
177	status = "okay";
178};
179
180&nandc0 {
181	u-boot,dm-spl;
182	status = "okay";
183	#address-cells = <1>;
184	#size-cells = <0>;
185	/delete-property/ pinctrl-names;
186	/delete-property/ pinctrl-0;
187
188	nand@0 {
189		u-boot,dm-spl;
190		reg = <0>;
191		nand-ecc-mode = "hw_syndrome";
192		nand-ecc-strength = <16>;
193		nand-ecc-step-size = <1024>;
194	};
195};
196
197&gmac0_clkin{
198	u-boot,dm-pre-reloc;
199};
200
201&gmac1_clkin {
202	u-boot,dm-pre-reloc;
203};
204
205&gmac0 {
206	u-boot,dm-pre-reloc;
207	phy-mode = "rgmii";
208	clock_in_out = "output";
209
210	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
211	snps,reset-active-low;
212	/* Reset time is 20ms, 100ms for rtl8211f */
213	snps,reset-delays-us = <0 20000 100000>;
214	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
215	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
216	assigned-clock-rates = <0>, <125000000>;
217
218	pinctrl-names = "default";
219	pinctrl-0 = <&gmac0_miim
220		     &gmac0_tx_bus2
221		     &gmac0_rx_bus2
222		     &gmac0_rgmii_clk
223		     &gmac0_rgmii_bus>;
224
225	tx_delay = <0x3c>;
226	rx_delay = <0x2f>;
227
228	phy-handle = <&rgmii_phy0>;
229	status = "disabled";
230};
231
232&gmac1 {
233	u-boot,dm-pre-reloc;
234	phy-mode = "rgmii";
235	clock_in_out = "output";
236
237	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
238	snps,reset-active-low;
239	/* Reset time is 20ms, 100ms for rtl8211f */
240	snps,reset-delays-us = <0 20000 100000>;
241
242	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
243	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
244	assigned-clock-rates = <0>, <125000000>;
245
246	pinctrl-names = "default";
247	pinctrl-0 = <&gmac1m1_miim
248		     &gmac1m1_tx_bus2
249		     &gmac1m1_rx_bus2
250		     &gmac1m1_rgmii_clk
251		     &gmac1m1_rgmii_bus>;
252
253	tx_delay = <0x4f>;
254	rx_delay = <0x26>;
255
256	phy-handle = <&rgmii_phy1>;
257	status = "disabled";
258};
259
260&gmac0_stmmac_axi_setup {
261	u-boot,dm-pre-reloc;
262};
263
264&gmac0_mtl_rx_setup {
265	u-boot,dm-pre-reloc;
266	queue0 {
267		u-boot,dm-pre-reloc;
268	};
269};
270
271&gmac0_mtl_tx_setup {
272	u-boot,dm-pre-reloc;
273	queue0 {
274		u-boot,dm-pre-reloc;
275	};
276};
277
278&gmac1_stmmac_axi_setup {
279	u-boot,dm-pre-reloc;
280};
281
282&gmac1_mtl_rx_setup {
283	u-boot,dm-pre-reloc;
284	queue0 {
285		u-boot,dm-pre-reloc;
286	};
287};
288
289&gmac1_mtl_tx_setup {
290	u-boot,dm-pre-reloc;
291	queue0 {
292		u-boot,dm-pre-reloc;
293	};
294};
295
296&mdio0 {
297	u-boot,dm-pre-reloc;
298	rgmii_phy0: phy@0 {
299		compatible = "ethernet-phy-ieee802.3-c22";
300		u-boot,dm-pre-reloc;
301		reg = <0x0>;
302	};
303};
304
305&mdio1 {
306	u-boot,dm-pre-reloc;
307	rgmii_phy1: phy@0 {
308		compatible = "ethernet-phy-ieee802.3-c22";
309		u-boot,dm-pre-reloc;
310		reg = <0x0>;
311	};
312};
313
314&gmac0_miim {
315	u-boot,dm-pre-reloc;
316};
317
318&gmac0_clkinout {
319	u-boot,dm-pre-reloc;
320};
321
322&gmac0_rx_bus2 {
323	u-boot,dm-pre-reloc;
324};
325
326&gmac0_tx_bus2 {
327	u-boot,dm-pre-reloc;
328};
329
330&gmac0_rgmii_clk {
331	u-boot,dm-pre-reloc;
332};
333
334&gmac0_rgmii_bus {
335	u-boot,dm-pre-reloc;
336};
337
338&gmac1m1_miim {
339	u-boot,dm-pre-reloc;
340};
341
342&gmac1m1_clkinout {
343	u-boot,dm-pre-reloc;
344};
345
346&gmac1m1_rx_bus2 {
347	u-boot,dm-pre-reloc;
348};
349
350&gmac1m1_tx_bus2 {
351	u-boot,dm-pre-reloc;
352};
353
354&gmac1m1_rgmii_clk {
355	u-boot,dm-pre-reloc;
356};
357
358&gmac1m1_rgmii_bus {
359	u-boot,dm-pre-reloc;
360};
361
362&eth0_clkout_pins {
363	u-boot,dm-pre-reloc;
364};
365
366&eth1m1_clkout_pins {
367	u-boot,dm-pre-reloc;
368};
369
370&pcie30phy {
371	u-boot,dm-pre-reloc;
372	status = "okay";
373};
374
375&pcie3x2 {
376	u-boot,dm-pre-reloc;
377	status = "okay";
378};
379
380&pinctrl {
381	u-boot,dm-pre-reloc;
382	status = "okay";
383};
384
385&gpio0 {
386	u-boot,dm-spl;
387};
388
389&gpio1 {
390	u-boot,dm-spl;
391};
392
393&gpio2 {
394	u-boot,dm-pre-reloc;
395};
396
397&pcfg_pull_none_drv_level_1 {
398	u-boot,dm-pre-reloc;
399};
400
401&pcfg_pull_none_drv_level_2 {
402	u-boot,dm-pre-reloc;
403};
404
405
406&pcfg_pull_up_drv_level_1 {
407	u-boot,dm-spl;
408};
409
410&pcfg_pull_up_drv_level_2 {
411	u-boot,dm-spl;
412};
413
414&pcfg_pull_up {
415	u-boot,dm-spl;
416};
417
418&pcfg_pull_none {
419	u-boot,dm-pre-reloc;
420};
421
422&secure_otp {
423	u-boot,dm-spl;
424};
425
426&wdt {
427	u-boot,dm-pre-reloc;
428	status = "okay";
429};
430