xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3568-u-boot.dtsi (revision 4b97f93074f3c3fd638fb1d4e20ff6639c142208) 
1/*
2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		ethernet0 = &gmac0;
10		ethernet1 = &gmac1;
11		mmc0 = &sdhci;
12		mmc1 = &sdmmc0;
13		mmc2 = &sdmmc1;
14	};
15
16	chosen {
17		stdout-path = &uart2;
18		u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
19	};
20
21	secure-otp@fe3a0000 {
22		compatible = "rockchip,rk3568-secure-otp";
23		reg = <0x0 0xfe3a0000 0x0 0x4000>;
24		secure_conf = <0xfdd18008>;
25		mask_addr = <0xfe880000>;
26		cru_rst_addr = <0xfdd20470>;
27		u-boot,dm-spl;
28	};
29};
30
31&psci {
32	u-boot,dm-pre-reloc;
33	status = "okay";
34};
35
36&crypto {
37	u-boot,dm-spl;
38};
39
40&uart2 {
41	clock-frequency = <24000000>;
42	u-boot,dm-spl;
43	/delete-property/ pinctrl-names;
44	/delete-property/ pinctrl-0;
45	status = "okay";
46};
47
48&grf {
49	u-boot,dm-spl;
50	status = "okay";
51};
52
53&pmugrf {
54	u-boot,dm-spl;
55	status = "okay";
56};
57
58&usb2phy0_grf {
59	u-boot,dm-pre-reloc;
60	status = "okay";
61};
62
63&usbdrd30 {
64	u-boot,dm-pre-reloc;
65	status = "okay";
66};
67
68&usbdrd_dwc3 {
69	u-boot,dm-pre-reloc;
70	status = "okay";
71};
72
73&usbhost30 {
74	u-boot,dm-pre-reloc;
75	status = "okay";
76};
77
78&usbhost_dwc3 {
79	u-boot,dm-pre-reloc;
80	status = "okay";
81};
82
83&usb2phy0 {
84	u-boot,dm-pre-reloc;
85	status = "okay";
86};
87
88&u2phy0_otg {
89	u-boot,dm-pre-reloc;
90	status = "okay";
91};
92
93&u2phy0_host {
94	u-boot,dm-pre-reloc;
95	status = "okay";
96};
97
98&cru {
99	u-boot,dm-spl;
100	status = "okay";
101};
102
103&pmucru {
104	u-boot,dm-spl;
105	status = "okay";
106};
107
108&rng {
109	u-boot,dm-pre-reloc;
110	status = "okay";
111};
112
113&sfc {
114	u-boot,dm-spl;
115	/delete-property/ pinctrl-names;
116	/delete-property/ pinctrl-0;
117	/delete-property/ assigned-clocks;
118	/delete-property/ assigned-clock-rates;
119	status = "okay";
120
121	#address-cells = <1>;
122	#size-cells = <0>;
123	spi_nand: flash@0 {
124		u-boot,dm-spl;
125		compatible = "spi-nand";
126		reg = <0>;
127		spi-tx-bus-width = <1>;
128		spi-rx-bus-width = <4>;
129		spi-max-frequency = <75000000>;
130	};
131
132	spi_nor: flash@1 {
133		u-boot,dm-spl;
134		compatible = "jedec,spi-nor";
135		label = "sfc_nor";
136		reg = <0>;
137		spi-tx-bus-width = <1>;
138		spi-rx-bus-width = <4>;
139		spi-max-frequency = <100000000>;
140	};
141};
142
143&saradc {
144	u-boot,dm-pre-reloc;
145	status = "okay";
146};
147
148&sdmmc0 {
149	u-boot,dm-spl;
150	status = "okay";
151};
152
153&sdmmc0_pins {
154	u-boot,dm-spl;
155};
156
157&sdmmc0_bus4 {
158	u-boot,dm-spl;
159};
160
161&sdmmc0_clk {
162	u-boot,dm-spl;
163};
164
165&sdmmc0_cmd {
166	u-boot,dm-spl;
167};
168
169&sdmmc0_det {
170	u-boot,dm-spl;
171};
172
173&sdmmc1 {
174	u-boot,dm-spl;
175	/delete-property/ pinctrl-names;
176	/delete-property/ pinctrl-0;
177	status = "okay";
178};
179
180&sdhci {
181	bus-width = <8>;
182	u-boot,dm-spl;
183	/delete-property/ pinctrl-names;
184	/delete-property/ pinctrl-0;
185	mmc-hs200-1_8v;
186	status = "okay";
187};
188
189&nandc0 {
190	u-boot,dm-spl;
191	status = "okay";
192	#address-cells = <1>;
193	#size-cells = <0>;
194	/delete-property/ pinctrl-names;
195	/delete-property/ pinctrl-0;
196
197	nand@0 {
198		u-boot,dm-spl;
199		reg = <0>;
200		nand-ecc-mode = "hw";
201		nand-ecc-strength = <16>;
202		nand-ecc-step-size = <1024>;
203	};
204};
205
206&gmac0_clkin {
207	u-boot,dm-pre-reloc;
208};
209
210&gmac1_clkin {
211	u-boot,dm-pre-reloc;
212};
213
214&gmac0 {
215	u-boot,dm-pre-reloc;
216	phy-mode = "rgmii";
217	clock_in_out = "output";
218
219	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
220	snps,reset-active-low;
221	/* Reset time is 20ms, 100ms for rtl8211f */
222	snps,reset-delays-us = <0 20000 100000>;
223	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
224	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
225	assigned-clock-rates = <0>, <125000000>;
226
227	pinctrl-names = "default";
228	pinctrl-0 = <&gmac0_miim
229		     &gmac0_tx_bus2
230		     &gmac0_rx_bus2
231		     &gmac0_rgmii_clk
232		     &gmac0_rgmii_bus>;
233
234	tx_delay = <0x3c>;
235	rx_delay = <0x2f>;
236
237	phy-handle = <&rgmii_phy0>;
238	status = "disabled";
239};
240
241&gmac1 {
242	u-boot,dm-pre-reloc;
243	phy-mode = "rgmii";
244	clock_in_out = "output";
245
246	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
247	snps,reset-active-low;
248	/* Reset time is 20ms, 100ms for rtl8211f */
249	snps,reset-delays-us = <0 20000 100000>;
250
251	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
252	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
253	assigned-clock-rates = <0>, <125000000>;
254
255	pinctrl-names = "default";
256	pinctrl-0 = <&gmac1m1_miim
257		     &gmac1m1_tx_bus2
258		     &gmac1m1_rx_bus2
259		     &gmac1m1_rgmii_clk
260		     &gmac1m1_rgmii_bus>;
261
262	tx_delay = <0x4f>;
263	rx_delay = <0x26>;
264
265	phy-handle = <&rgmii_phy1>;
266	status = "disabled";
267};
268
269&gmac0_stmmac_axi_setup {
270	u-boot,dm-pre-reloc;
271};
272
273&gmac0_mtl_rx_setup {
274	u-boot,dm-pre-reloc;
275	queue0 {
276		u-boot,dm-pre-reloc;
277	};
278};
279
280&gmac0_mtl_tx_setup {
281	u-boot,dm-pre-reloc;
282	queue0 {
283		u-boot,dm-pre-reloc;
284	};
285};
286
287&gmac1_stmmac_axi_setup {
288	u-boot,dm-pre-reloc;
289};
290
291&gmac1_mtl_rx_setup {
292	u-boot,dm-pre-reloc;
293	queue0 {
294		u-boot,dm-pre-reloc;
295	};
296};
297
298&gmac1_mtl_tx_setup {
299	u-boot,dm-pre-reloc;
300	queue0 {
301		u-boot,dm-pre-reloc;
302	};
303};
304
305&mdio0 {
306	u-boot,dm-pre-reloc;
307	rgmii_phy0: phy@0 {
308		compatible = "ethernet-phy-ieee802.3-c22";
309		u-boot,dm-pre-reloc;
310		reg = <0x0>;
311	};
312};
313
314&mdio1 {
315	u-boot,dm-pre-reloc;
316	rgmii_phy1: phy@0 {
317		compatible = "ethernet-phy-ieee802.3-c22";
318		u-boot,dm-pre-reloc;
319		reg = <0x0>;
320	};
321};
322
323&gmac0_miim {
324	u-boot,dm-pre-reloc;
325};
326
327&gmac0_clkinout {
328	u-boot,dm-pre-reloc;
329};
330
331&gmac0_rx_bus2 {
332	u-boot,dm-pre-reloc;
333};
334
335&gmac0_tx_bus2 {
336	u-boot,dm-pre-reloc;
337};
338
339&gmac0_rgmii_clk {
340	u-boot,dm-pre-reloc;
341};
342
343&gmac0_rgmii_bus {
344	u-boot,dm-pre-reloc;
345};
346
347&gmac1m1_miim {
348	u-boot,dm-pre-reloc;
349};
350
351&gmac1m1_clkinout {
352	u-boot,dm-pre-reloc;
353};
354
355&gmac1m1_rx_bus2 {
356	u-boot,dm-pre-reloc;
357};
358
359&gmac1m1_tx_bus2 {
360	u-boot,dm-pre-reloc;
361};
362
363&gmac1m1_rgmii_clk {
364	u-boot,dm-pre-reloc;
365};
366
367&gmac1m1_rgmii_bus {
368	u-boot,dm-pre-reloc;
369};
370
371&eth0_clkout_pins {
372	u-boot,dm-pre-reloc;
373};
374
375&eth1m1_clkout_pins {
376	u-boot,dm-pre-reloc;
377};
378
379&pcie30phy {
380	u-boot,dm-pre-reloc;
381	status = "okay";
382};
383
384&pcie3x2 {
385	u-boot,dm-pre-reloc;
386	status = "okay";
387};
388
389&pinctrl {
390	u-boot,dm-pre-reloc;
391	status = "okay";
392};
393
394&gpio0 {
395	u-boot,dm-spl;
396};
397
398&gpio1 {
399	u-boot,dm-spl;
400};
401
402&gpio2 {
403	u-boot,dm-spl;
404};
405
406&pcfg_pull_none_drv_level_1 {
407	u-boot,dm-spl;
408};
409
410&pcfg_pull_none_drv_level_2 {
411	u-boot,dm-spl;
412};
413
414
415&pcfg_pull_up_drv_level_1 {
416	u-boot,dm-spl;
417};
418
419&pcfg_pull_up_drv_level_2 {
420	u-boot,dm-spl;
421};
422
423&pcfg_pull_up {
424	u-boot,dm-spl;
425};
426
427&pcfg_pull_none {
428	u-boot,dm-spl;
429};
430
431&wdt {
432	u-boot,dm-pre-reloc;
433	status = "okay";
434};
435
436#if 0
437&i2c0 {
438	u-boot,dm-pre-reloc;
439	status = "okay";
440};
441
442&i2c0_xfer {
443	u-boot,dm-pre-reloc;
444	status = "okay";
445};
446
447&i2c1 {
448	u-boot,dm-pre-reloc;
449	status = "okay";
450};
451
452&i2c1_xfer {
453	u-boot,dm-pre-reloc;
454	status = "okay";
455};
456
457&pcfg_pull_none_smt {
458	u-boot,dm-pre-reloc;
459	status = "okay";
460};
461#endif
462
463