xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3568-u-boot.dtsi (revision 2f6c020d95ebda22b28d3a31f574ec547a9281fb) 
1/*
2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		ethernet0 = &gmac0;
10		ethernet1 = &gmac1;
11		mmc0 = &sdhci;
12		mmc1 = &sdmmc0;
13		mmc2 = &sdmmc1;
14	};
15
16	chosen {
17		stdout-path = &uart2;
18		u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
19	};
20
21	secure-otp@fe3a0000 {
22		compatible = "rockchip,rk3568-secure-otp";
23		reg = <0x0 0xfe3a0000 0x0 0x4000>;
24		secure_conf = <0xfdd18008>;
25		mask_addr = <0xfe880000>;
26		cru_rst_addr = <0xfdd20470>;
27		u-boot,dm-spl;
28	};
29};
30
31&psci {
32	u-boot,dm-pre-reloc;
33	status = "okay";
34};
35
36&combphy0_us {
37	u-boot,dm-pre-reloc;
38	status = "okay";
39};
40
41&crypto {
42	u-boot,dm-spl;
43};
44
45&uart2 {
46	clock-frequency = <24000000>;
47	u-boot,dm-spl;
48	/delete-property/ pinctrl-names;
49	/delete-property/ pinctrl-0;
50	status = "okay";
51};
52
53&grf {
54	u-boot,dm-spl;
55	status = "okay";
56};
57
58&pipegrf {
59	u-boot,dm-pre-reloc;
60};
61
62&pipe_phy_grf0 {
63	u-boot,dm-pre-reloc;
64};
65
66&pmugrf {
67	u-boot,dm-spl;
68	status = "okay";
69};
70
71&usb2phy0_grf {
72	u-boot,dm-pre-reloc;
73	status = "okay";
74};
75
76&usbdrd30 {
77	u-boot,dm-pre-reloc;
78	status = "okay";
79};
80
81&usbdrd_dwc3 {
82	u-boot,dm-pre-reloc;
83	status = "okay";
84};
85
86&usbhost30 {
87	u-boot,dm-pre-reloc;
88	status = "okay";
89};
90
91&usbhost_dwc3 {
92	u-boot,dm-pre-reloc;
93	status = "okay";
94};
95
96&usb2phy0 {
97	u-boot,dm-pre-reloc;
98	status = "okay";
99};
100
101&u2phy0_otg {
102	u-boot,dm-pre-reloc;
103	status = "okay";
104};
105
106&u2phy0_host {
107	u-boot,dm-pre-reloc;
108	status = "okay";
109};
110
111&cru {
112	u-boot,dm-spl;
113	status = "okay";
114};
115
116&pmucru {
117	u-boot,dm-spl;
118	status = "okay";
119};
120
121&rng {
122	u-boot,dm-pre-reloc;
123	status = "okay";
124};
125
126&sfc {
127	u-boot,dm-spl;
128	/delete-property/ pinctrl-names;
129	/delete-property/ pinctrl-0;
130	/delete-property/ assigned-clocks;
131	/delete-property/ assigned-clock-rates;
132	status = "okay";
133
134	#address-cells = <1>;
135	#size-cells = <0>;
136	spi_nand: flash@0 {
137		u-boot,dm-spl;
138		compatible = "spi-nand";
139		reg = <0>;
140		spi-tx-bus-width = <1>;
141		spi-rx-bus-width = <4>;
142		spi-max-frequency = <75000000>;
143	};
144
145	spi_nor: flash@1 {
146		u-boot,dm-spl;
147		compatible = "jedec,spi-nor";
148		label = "sfc_nor";
149		reg = <0>;
150		spi-tx-bus-width = <1>;
151		spi-rx-bus-width = <4>;
152		spi-max-frequency = <100000000>;
153	};
154};
155
156&saradc {
157	u-boot,dm-pre-reloc;
158	status = "okay";
159};
160
161&sdmmc0 {
162	u-boot,dm-spl;
163	status = "okay";
164};
165
166&sdmmc0_pins {
167	u-boot,dm-spl;
168};
169
170&sdmmc0_bus4 {
171	u-boot,dm-spl;
172};
173
174&sdmmc0_clk {
175	u-boot,dm-spl;
176};
177
178&sdmmc0_cmd {
179	u-boot,dm-spl;
180};
181
182&sdmmc0_det {
183	u-boot,dm-spl;
184};
185
186&sdmmc1 {
187	u-boot,dm-spl;
188	/delete-property/ pinctrl-names;
189	/delete-property/ pinctrl-0;
190	status = "okay";
191};
192
193&sdhci {
194	bus-width = <8>;
195	u-boot,dm-spl;
196	/delete-property/ pinctrl-names;
197	/delete-property/ pinctrl-0;
198	mmc-hs200-1_8v;
199	status = "okay";
200};
201
202&nandc0 {
203	u-boot,dm-spl;
204	status = "okay";
205	#address-cells = <1>;
206	#size-cells = <0>;
207	/delete-property/ pinctrl-names;
208	/delete-property/ pinctrl-0;
209
210	nand@0 {
211		u-boot,dm-spl;
212		reg = <0>;
213		nand-ecc-mode = "hw";
214		nand-ecc-strength = <16>;
215		nand-ecc-step-size = <1024>;
216	};
217};
218
219&gmac0_clkin {
220	u-boot,dm-pre-reloc;
221};
222
223&gmac1_clkin {
224	u-boot,dm-pre-reloc;
225};
226
227&gmac0 {
228	u-boot,dm-pre-reloc;
229	phy-mode = "rgmii";
230	clock_in_out = "output";
231
232	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
233	snps,reset-active-low;
234	/* Reset time is 20ms, 100ms for rtl8211f */
235	snps,reset-delays-us = <0 20000 100000>;
236	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
237	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
238	assigned-clock-rates = <0>, <125000000>;
239
240	pinctrl-names = "default";
241	pinctrl-0 = <&gmac0_miim
242		     &gmac0_tx_bus2
243		     &gmac0_rx_bus2
244		     &gmac0_rgmii_clk
245		     &gmac0_rgmii_bus>;
246
247	tx_delay = <0x3c>;
248	rx_delay = <0x2f>;
249
250	phy-handle = <&rgmii_phy0>;
251	status = "disabled";
252};
253
254&gmac1 {
255	u-boot,dm-pre-reloc;
256	phy-mode = "rgmii";
257	clock_in_out = "output";
258
259	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
260	snps,reset-active-low;
261	/* Reset time is 20ms, 100ms for rtl8211f */
262	snps,reset-delays-us = <0 20000 100000>;
263
264	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
265	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
266	assigned-clock-rates = <0>, <125000000>;
267
268	pinctrl-names = "default";
269	pinctrl-0 = <&gmac1m1_miim
270		     &gmac1m1_tx_bus2
271		     &gmac1m1_rx_bus2
272		     &gmac1m1_rgmii_clk
273		     &gmac1m1_rgmii_bus>;
274
275	tx_delay = <0x4f>;
276	rx_delay = <0x26>;
277
278	phy-handle = <&rgmii_phy1>;
279	status = "disabled";
280};
281
282&gmac0_stmmac_axi_setup {
283	u-boot,dm-pre-reloc;
284};
285
286&gmac0_mtl_rx_setup {
287	u-boot,dm-pre-reloc;
288	queue0 {
289		u-boot,dm-pre-reloc;
290	};
291};
292
293&gmac0_mtl_tx_setup {
294	u-boot,dm-pre-reloc;
295	queue0 {
296		u-boot,dm-pre-reloc;
297	};
298};
299
300&gmac1_stmmac_axi_setup {
301	u-boot,dm-pre-reloc;
302};
303
304&gmac1_mtl_rx_setup {
305	u-boot,dm-pre-reloc;
306	queue0 {
307		u-boot,dm-pre-reloc;
308	};
309};
310
311&gmac1_mtl_tx_setup {
312	u-boot,dm-pre-reloc;
313	queue0 {
314		u-boot,dm-pre-reloc;
315	};
316};
317
318&mdio0 {
319	u-boot,dm-pre-reloc;
320	rgmii_phy0: phy@0 {
321		compatible = "ethernet-phy-ieee802.3-c22";
322		u-boot,dm-pre-reloc;
323		reg = <0x0>;
324	};
325};
326
327&mdio1 {
328	u-boot,dm-pre-reloc;
329	rgmii_phy1: phy@0 {
330		compatible = "ethernet-phy-ieee802.3-c22";
331		u-boot,dm-pre-reloc;
332		reg = <0x0>;
333	};
334};
335
336&gmac0_miim {
337	u-boot,dm-pre-reloc;
338};
339
340&gmac0_clkinout {
341	u-boot,dm-pre-reloc;
342};
343
344&gmac0_rx_bus2 {
345	u-boot,dm-pre-reloc;
346};
347
348&gmac0_tx_bus2 {
349	u-boot,dm-pre-reloc;
350};
351
352&gmac0_rgmii_clk {
353	u-boot,dm-pre-reloc;
354};
355
356&gmac0_rgmii_bus {
357	u-boot,dm-pre-reloc;
358};
359
360&gmac1m1_miim {
361	u-boot,dm-pre-reloc;
362};
363
364&gmac1m1_clkinout {
365	u-boot,dm-pre-reloc;
366};
367
368&gmac1m1_rx_bus2 {
369	u-boot,dm-pre-reloc;
370};
371
372&gmac1m1_tx_bus2 {
373	u-boot,dm-pre-reloc;
374};
375
376&gmac1m1_rgmii_clk {
377	u-boot,dm-pre-reloc;
378};
379
380&gmac1m1_rgmii_bus {
381	u-boot,dm-pre-reloc;
382};
383
384&eth0_clkout_pins {
385	u-boot,dm-pre-reloc;
386};
387
388&eth1m1_clkout_pins {
389	u-boot,dm-pre-reloc;
390};
391
392&pcie30phy {
393	u-boot,dm-pre-reloc;
394	status = "okay";
395};
396
397&pcie3x2 {
398	u-boot,dm-pre-reloc;
399	status = "okay";
400};
401
402&pinctrl {
403	u-boot,dm-spl;
404	status = "okay";
405};
406
407&gpio0 {
408	u-boot,dm-spl;
409};
410
411&gpio1 {
412	u-boot,dm-spl;
413};
414
415&gpio2 {
416	u-boot,dm-spl;
417};
418
419&pcfg_pull_none_drv_level_1 {
420	u-boot,dm-spl;
421};
422
423&pcfg_pull_none_drv_level_2 {
424	u-boot,dm-spl;
425};
426
427
428&pcfg_pull_up_drv_level_1 {
429	u-boot,dm-spl;
430};
431
432&pcfg_pull_up_drv_level_2 {
433	u-boot,dm-spl;
434};
435
436&pcfg_pull_up {
437	u-boot,dm-spl;
438};
439
440&pcfg_pull_none {
441	u-boot,dm-spl;
442};
443
444&wdt {
445	u-boot,dm-pre-reloc;
446	status = "okay";
447};
448
449#if 0
450&i2c0 {
451	u-boot,dm-pre-reloc;
452	status = "okay";
453};
454
455&i2c0_xfer {
456	u-boot,dm-pre-reloc;
457	status = "okay";
458};
459
460&i2c1 {
461	u-boot,dm-pre-reloc;
462	status = "okay";
463};
464
465&i2c1_xfer {
466	u-boot,dm-pre-reloc;
467	status = "okay";
468};
469
470&pcfg_pull_none_smt {
471	u-boot,dm-pre-reloc;
472	status = "okay";
473};
474#endif
475
476