xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3568-u-boot.dtsi (revision 2a7051be6cb4eddfbb7c8a7288750ec77adc42f3) 
1/*
2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		ethernet0 = &gmac0;
10		ethernet1 = &gmac1;
11		mmc0 = &sdhci;
12		mmc1 = &sdmmc0;
13		mmc2 = &sdmmc1;
14	};
15
16	chosen {
17		stdout-path = &uart2;
18		u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
19	};
20};
21
22&crypto {
23	u-boot,dm-pre-reloc;
24};
25
26&uart2 {
27	clock-frequency = <24000000>;
28	u-boot,dm-spl;
29	/delete-property/ pinctrl-names;
30	/delete-property/ pinctrl-0;
31	status = "okay";
32};
33
34&grf {
35	u-boot,dm-pre-reloc;
36	status = "okay";
37};
38
39&pmugrf {
40	u-boot,dm-pre-reloc;
41	status = "okay";
42};
43
44&usb2phy0_grf {
45	u-boot,dm-pre-reloc;
46	status = "okay";
47};
48
49&usbdrd30 {
50	u-boot,dm-pre-reloc;
51	status = "okay";
52};
53
54&usbdrd_dwc3 {
55	u-boot,dm-pre-reloc;
56	status = "okay";
57};
58
59&usbhost30 {
60	u-boot,dm-pre-reloc;
61	status = "okay";
62};
63
64&usbhost_dwc3 {
65	u-boot,dm-pre-reloc;
66	status = "okay";
67};
68
69&usb2phy0 {
70	u-boot,dm-pre-reloc;
71	status = "okay";
72};
73
74&u2phy0_otg {
75	u-boot,dm-pre-reloc;
76	status = "okay";
77};
78
79&u2phy0_host {
80	u-boot,dm-pre-reloc;
81	status = "okay";
82};
83
84&cru {
85	u-boot,dm-pre-reloc;
86	status = "okay";
87};
88
89&pmucru {
90	u-boot,dm-pre-reloc;
91	status = "okay";
92};
93
94&sfc {
95	u-boot,dm-spl;
96	/delete-property/ pinctrl-names;
97	/delete-property/ pinctrl-0;
98	/delete-property/ assigned-clocks;
99	/delete-property/ assigned-clock-rates;
100	status = "okay";
101
102	#address-cells = <1>;
103	#size-cells = <0>;
104	spi_nand: flash@0 {
105		u-boot,dm-spl;
106		compatible = "spi-nand";
107		reg = <0>;
108		spi-tx-bus-width = <1>;
109		spi-rx-bus-width = <4>;
110		spi-max-frequency = <96000000>;
111	};
112
113	spi_nor: flash@1 {
114		u-boot,dm-spl;
115		compatible = "jedec,spi-nor";
116		label = "sfc_nor";
117		reg = <0>;
118		spi-tx-bus-width = <1>;
119		spi-rx-bus-width = <4>;
120		spi-max-frequency = <100000000>;
121	};
122};
123
124&saradc {
125	u-boot,dm-spl;
126	status = "okay";
127};
128
129&sdmmc0 {
130	u-boot,dm-spl;
131	status = "okay";
132};
133
134&sdmmc0_pins {
135	u-boot,dm-spl;
136};
137
138&sdmmc0_bus4 {
139	u-boot,dm-spl;
140};
141
142&sdmmc0_clk {
143	u-boot,dm-spl;
144};
145
146&sdmmc0_cmd {
147	u-boot,dm-spl;
148};
149
150&sdmmc0_det {
151	u-boot,dm-spl;
152};
153
154&sdmmc1 {
155	u-boot,dm-spl;
156	/delete-property/ pinctrl-names;
157	/delete-property/ pinctrl-0;
158	status = "okay";
159};
160
161&sdhci {
162	bus-width = <8>;
163	u-boot,dm-spl;
164	/delete-property/ pinctrl-names;
165	/delete-property/ pinctrl-0;
166	mmc-hs200-1_8v;
167	status = "okay";
168};
169
170&nandc0 {
171	u-boot,dm-spl;
172	status = "okay";
173	#address-cells = <1>;
174	#size-cells = <0>;
175	/delete-property/ pinctrl-names;
176	/delete-property/ pinctrl-0;
177
178	nand@0 {
179		u-boot,dm-spl;
180		reg = <0>;
181		nand-ecc-mode = "hw_syndrome";
182		nand-ecc-strength = <16>;
183		nand-ecc-step-size = <1024>;
184	};
185};
186
187&gmac0_clkin{
188	u-boot,dm-pre-reloc;
189};
190
191&gmac1_clkin {
192	u-boot,dm-pre-reloc;
193};
194
195&gmac0 {
196	u-boot,dm-pre-reloc;
197	phy-mode = "rgmii";
198	clock_in_out = "output";
199
200	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
201	snps,reset-active-low;
202	/* Reset time is 20ms, 100ms for rtl8211f */
203	snps,reset-delays-us = <0 20000 100000>;
204	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
205	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
206	assigned-clock-rates = <0>, <125000000>;
207
208	pinctrl-names = "default";
209	pinctrl-0 = <&gmac0_miim
210		     &gmac0_tx_bus2
211		     &gmac0_rx_bus2
212		     &gmac0_rgmii_clk
213		     &gmac0_rgmii_bus>;
214
215	tx_delay = <0x3c>;
216	rx_delay = <0x2f>;
217
218	phy-handle = <&rgmii_phy0>;
219	status = "disabled";
220};
221
222&gmac1 {
223	u-boot,dm-pre-reloc;
224	phy-mode = "rgmii";
225	clock_in_out = "output";
226
227	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
228	snps,reset-active-low;
229	/* Reset time is 20ms, 100ms for rtl8211f */
230	snps,reset-delays-us = <0 20000 100000>;
231
232	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
233	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
234	assigned-clock-rates = <0>, <125000000>;
235
236	pinctrl-names = "default";
237	pinctrl-0 = <&gmac1m1_miim
238		     &gmac1m1_tx_bus2
239		     &gmac1m1_rx_bus2
240		     &gmac1m1_rgmii_clk
241		     &gmac1m1_rgmii_bus>;
242
243	tx_delay = <0x4f>;
244	rx_delay = <0x26>;
245
246	phy-handle = <&rgmii_phy1>;
247	status = "disabled";
248};
249
250&gmac0_stmmac_axi_setup {
251	u-boot,dm-pre-reloc;
252};
253
254&gmac0_mtl_rx_setup {
255	u-boot,dm-pre-reloc;
256	queue0 {
257		u-boot,dm-pre-reloc;
258	};
259};
260
261&gmac0_mtl_tx_setup {
262	u-boot,dm-pre-reloc;
263	queue0 {
264		u-boot,dm-pre-reloc;
265	};
266};
267
268&gmac1_stmmac_axi_setup {
269	u-boot,dm-pre-reloc;
270};
271
272&gmac1_mtl_rx_setup {
273	u-boot,dm-pre-reloc;
274	queue0 {
275		u-boot,dm-pre-reloc;
276	};
277};
278
279&gmac1_mtl_tx_setup {
280	u-boot,dm-pre-reloc;
281	queue0 {
282		u-boot,dm-pre-reloc;
283	};
284};
285
286&mdio0 {
287	u-boot,dm-pre-reloc;
288	rgmii_phy0: phy@0 {
289		compatible = "ethernet-phy-ieee802.3-c22";
290		u-boot,dm-pre-reloc;
291		reg = <0x0>;
292	};
293};
294
295&mdio1 {
296	u-boot,dm-pre-reloc;
297	rgmii_phy1: phy@0 {
298		compatible = "ethernet-phy-ieee802.3-c22";
299		u-boot,dm-pre-reloc;
300		reg = <0x0>;
301	};
302};
303
304&gmac0_miim {
305	u-boot,dm-pre-reloc;
306};
307
308&gmac0_clkinout {
309	u-boot,dm-pre-reloc;
310};
311
312&gmac0_rx_bus2 {
313	u-boot,dm-pre-reloc;
314};
315
316&gmac0_tx_bus2 {
317	u-boot,dm-pre-reloc;
318};
319
320&gmac0_rgmii_clk {
321	u-boot,dm-pre-reloc;
322};
323
324&gmac0_rgmii_bus {
325	u-boot,dm-pre-reloc;
326};
327
328&gmac1m1_miim {
329	u-boot,dm-pre-reloc;
330};
331
332&gmac1m1_clkinout {
333	u-boot,dm-pre-reloc;
334};
335
336&gmac1m1_rx_bus2 {
337	u-boot,dm-pre-reloc;
338};
339
340&gmac1m1_tx_bus2 {
341	u-boot,dm-pre-reloc;
342};
343
344&gmac1m1_rgmii_clk {
345	u-boot,dm-pre-reloc;
346};
347
348&gmac1m1_rgmii_bus {
349	u-boot,dm-pre-reloc;
350};
351
352&eth0_clkout_pins {
353	u-boot,dm-pre-reloc;
354};
355
356&eth1m1_clkout_pins {
357	u-boot,dm-pre-reloc;
358};
359
360&pcie30phy {
361	u-boot,dm-pre-reloc;
362	status = "okay";
363};
364
365&pcie3x2 {
366	u-boot,dm-pre-reloc;
367	status = "okay";
368};
369
370&pinctrl {
371	u-boot,dm-pre-reloc;
372	status = "okay";
373};
374
375&gpio0 {
376	u-boot,dm-spl;
377};
378
379&gpio1 {
380	u-boot,dm-spl;
381};
382
383&gpio2 {
384	u-boot,dm-pre-reloc;
385};
386
387&pcfg_pull_none_drv_level_1 {
388	u-boot,dm-pre-reloc;
389};
390
391&pcfg_pull_none_drv_level_2 {
392	u-boot,dm-pre-reloc;
393};
394
395
396&pcfg_pull_up_drv_level_1 {
397	u-boot,dm-spl;
398};
399
400&pcfg_pull_up_drv_level_2 {
401	u-boot,dm-spl;
402};
403
404&pcfg_pull_up {
405	u-boot,dm-spl;
406};
407
408&pcfg_pull_none {
409	u-boot,dm-pre-reloc;
410};
411
412&secure_otp {
413	u-boot,dm-spl;
414};
415
416&wdt {
417	u-boot,dm-pre-reloc;
418	status = "okay";
419};
420