1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3368-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/thermal/thermal.h> 49#include <dt-bindings/memory/rk3368-dmc.h> 50 51/ { 52 compatible = "rockchip,rk3368"; 53 interrupt-parent = <&gic>; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 57 aliases { 58 ethernet0 = &gmac; 59 i2c0 = &i2c0; 60 i2c1 = &i2c1; 61 i2c2 = &i2c2; 62 i2c3 = &i2c3; 63 i2c4 = &i2c4; 64 i2c5 = &i2c5; 65 serial0 = &uart0; 66 serial1 = &uart1; 67 serial2 = &uart2; 68 serial3 = &uart3; 69 serial4 = &uart4; 70 spi0 = &spi0; 71 spi1 = &spi1; 72 spi2 = &spi2; 73 }; 74 75 cpus { 76 #address-cells = <0x2>; 77 #size-cells = <0x0>; 78 79 cpu-map { 80 cluster0 { 81 core0 { 82 cpu = <&cpu_b0>; 83 }; 84 core1 { 85 cpu = <&cpu_b1>; 86 }; 87 core2 { 88 cpu = <&cpu_b2>; 89 }; 90 core3 { 91 cpu = <&cpu_b3>; 92 }; 93 }; 94 95 cluster1 { 96 core0 { 97 cpu = <&cpu_l0>; 98 }; 99 core1 { 100 cpu = <&cpu_l1>; 101 }; 102 core2 { 103 cpu = <&cpu_l2>; 104 }; 105 core3 { 106 cpu = <&cpu_l3>; 107 }; 108 }; 109 }; 110 111 idle-states { 112 entry-method = "psci"; 113 114 cpu_sleep: cpu-sleep-0 { 115 compatible = "arm,idle-state"; 116 arm,psci-suspend-param = <0x1010000>; 117 entry-latency-us = <0x3fffffff>; 118 exit-latency-us = <0x40000000>; 119 min-residency-us = <0xffffffff>; 120 }; 121 }; 122 123 cpu_l0: cpu@0 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a53", "arm,armv8"; 126 reg = <0x0 0x0>; 127 cpu-idle-states = <&cpu_sleep>; 128 enable-method = "psci"; 129 130 #cooling-cells = <2>; /* min followed by max */ 131 }; 132 133 cpu_l1: cpu@1 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53", "arm,armv8"; 136 reg = <0x0 0x1>; 137 cpu-idle-states = <&cpu_sleep>; 138 enable-method = "psci"; 139 }; 140 141 cpu_l2: cpu@2 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-a53", "arm,armv8"; 144 reg = <0x0 0x2>; 145 cpu-idle-states = <&cpu_sleep>; 146 enable-method = "psci"; 147 }; 148 149 cpu_l3: cpu@3 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a53", "arm,armv8"; 152 reg = <0x0 0x3>; 153 cpu-idle-states = <&cpu_sleep>; 154 enable-method = "psci"; 155 }; 156 157 cpu_b0: cpu@100 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a53", "arm,armv8"; 160 reg = <0x0 0x100>; 161 cpu-idle-states = <&cpu_sleep>; 162 enable-method = "psci"; 163 164 #cooling-cells = <2>; /* min followed by max */ 165 }; 166 167 cpu_b1: cpu@101 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a53", "arm,armv8"; 170 reg = <0x0 0x101>; 171 cpu-idle-states = <&cpu_sleep>; 172 enable-method = "psci"; 173 }; 174 175 cpu_b2: cpu@102 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a53", "arm,armv8"; 178 reg = <0x0 0x102>; 179 cpu-idle-states = <&cpu_sleep>; 180 enable-method = "psci"; 181 }; 182 183 cpu_b3: cpu@103 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a53", "arm,armv8"; 186 reg = <0x0 0x103>; 187 cpu-idle-states = <&cpu_sleep>; 188 enable-method = "psci"; 189 }; 190 }; 191 192 arm-pmu { 193 compatible = "arm,armv8-pmuv3"; 194 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 203 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 204 <&cpu_b2>, <&cpu_b3>; 205 }; 206 207 psci { 208 compatible = "arm,psci-0.2"; 209 method = "smc"; 210 }; 211 212 timer { 213 compatible = "arm,armv8-timer"; 214 interrupts = <GIC_PPI 13 215 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 216 <GIC_PPI 14 217 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 218 <GIC_PPI 11 219 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 220 <GIC_PPI 10 221 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 222 }; 223 224 xin24m: oscillator { 225 compatible = "fixed-clock"; 226 clock-frequency = <24000000>; 227 clock-output-names = "xin24m"; 228 #clock-cells = <0>; 229 }; 230 231 dmc: dmc@ff610000 { 232 compatible = "rockchip,rk3368-dmc", "syscon"; 233 rockchip,cru = <&cru>; 234 rockchip,grf = <&grf>; 235 rockchip,msch = <&service_msch>; 236 reg = <0 0xff610000 0 0x400 237 0 0xff620000 0 0x400>; 238 }; 239 240 service_msch: syscon@ffac0000 { 241 compatible = "rockchip,rk3368-msch", "syscon"; 242 reg = <0x0 0xffac0000 0x0 0x2000>; 243 status = "okay"; 244 }; 245 246 sdmmc: dwmmc@ff0c0000 { 247 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 248 reg = <0x0 0xff0c0000 0x0 0x4000>; 249 clock-freq-min-max = <400000 150000000>; 250 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 251 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 252 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 253 fifo-depth = <0x100>; 254 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 255 status = "disabled"; 256 }; 257 258 sdio0: dwmmc@ff0d0000 { 259 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 260 reg = <0x0 0xff0d0000 0x0 0x4000>; 261 clock-freq-min-max = <400000 150000000>; 262 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 263 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 264 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 265 fifo-depth = <0x100>; 266 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 267 status = "disabled"; 268 }; 269 270 emmc: dwmmc@ff0f0000 { 271 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 272 reg = <0x0 0xff0f0000 0x0 0x4000>; 273 clock-freq-min-max = <400000 150000000>; 274 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 275 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 277 fifo-depth = <0x100>; 278 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 279 status = "disabled"; 280 }; 281 282 saradc: saradc@ff100000 { 283 compatible = "rockchip,saradc"; 284 reg = <0x0 0xff100000 0x0 0x100>; 285 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 286 #io-channel-cells = <1>; 287 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 288 clock-names = "saradc", "apb_pclk"; 289 status = "disabled"; 290 }; 291 292 spi0: spi@ff110000 { 293 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 294 reg = <0x0 0xff110000 0x0 0x1000>; 295 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 296 clock-names = "spiclk", "apb_pclk"; 297 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 status = "disabled"; 303 }; 304 305 spi1: spi@ff120000 { 306 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 307 reg = <0x0 0xff120000 0x0 0x1000>; 308 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 309 clock-names = "spiclk", "apb_pclk"; 310 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 }; 317 318 spi2: spi@ff130000 { 319 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 320 reg = <0x0 0xff130000 0x0 0x1000>; 321 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 322 clock-names = "spiclk", "apb_pclk"; 323 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 i2c1: i2c@ff140000 { 332 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 333 reg = <0x0 0xff140000 0x0 0x1000>; 334 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 clock-names = "i2c"; 338 clocks = <&cru PCLK_I2C1>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&i2c1_xfer>; 341 status = "disabled"; 342 }; 343 344 i2c3: i2c@ff150000 { 345 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 346 reg = <0x0 0xff150000 0x0 0x1000>; 347 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 clock-names = "i2c"; 351 clocks = <&cru PCLK_I2C3>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&i2c3_xfer>; 354 status = "disabled"; 355 }; 356 357 i2c4: i2c@ff160000 { 358 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 359 reg = <0x0 0xff160000 0x0 0x1000>; 360 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 clock-names = "i2c"; 364 clocks = <&cru PCLK_I2C4>; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&i2c4_xfer>; 367 status = "disabled"; 368 }; 369 370 i2c5: i2c@ff170000 { 371 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 372 reg = <0x0 0xff170000 0x0 0x1000>; 373 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 clock-names = "i2c"; 377 clocks = <&cru PCLK_I2C5>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&i2c5_xfer>; 380 status = "disabled"; 381 }; 382 383 nandc0: nandc@ff400000 { 384 compatible = "rockchip,rk-nandc"; 385 reg = <0x0 0xff400000 0x0 0x4000>; 386 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 387 nandc_id = <0>; 388 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>; 389 clock-names = "clk_nandc", "hclk_nandc"; 390 status = "disabled"; 391 }; 392 393 uart0: serial@ff180000 { 394 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 395 reg = <0x0 0xff180000 0x0 0x100>; 396 clock-frequency = <24000000>; 397 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 398 clock-names = "baudclk", "apb_pclk"; 399 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 400 reg-shift = <2>; 401 reg-io-width = <4>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&uart0_xfer>; 404 status = "disabled"; 405 }; 406 407 uart1: serial@ff190000 { 408 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 409 reg = <0x0 0xff190000 0x0 0x100>; 410 clock-frequency = <24000000>; 411 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 412 clock-names = "baudclk", "apb_pclk"; 413 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 414 reg-shift = <2>; 415 reg-io-width = <4>; 416 pinctrl-names = "default"; 417 pinctrl-1 = <&uart0_xfer>; 418 status = "disabled"; 419 }; 420 421 uart3: serial@ff1b0000 { 422 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 423 reg = <0x0 0xff1b0000 0x0 0x100>; 424 clock-frequency = <24000000>; 425 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 426 clock-names = "baudclk", "apb_pclk"; 427 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 428 reg-shift = <2>; 429 reg-io-width = <4>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&uart3_xfer>; 432 status = "disabled"; 433 }; 434 435 uart4: serial@ff1c0000 { 436 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 437 reg = <0x0 0xff1c0000 0x0 0x100>; 438 clock-frequency = <24000000>; 439 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 440 clock-names = "baudclk", "apb_pclk"; 441 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 442 reg-shift = <2>; 443 reg-io-width = <4>; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&uart4_xfer>; 446 status = "disabled"; 447 }; 448 449 thermal-zones { 450 cpu { 451 polling-delay-passive = <100>; /* milliseconds */ 452 polling-delay = <5000>; /* milliseconds */ 453 454 thermal-sensors = <&tsadc 0>; 455 456 trips { 457 cpu_alert0: cpu_alert0 { 458 temperature = <75000>; /* millicelsius */ 459 hysteresis = <2000>; /* millicelsius */ 460 type = "passive"; 461 }; 462 cpu_alert1: cpu_alert1 { 463 temperature = <80000>; /* millicelsius */ 464 hysteresis = <2000>; /* millicelsius */ 465 type = "passive"; 466 }; 467 cpu_crit: cpu_crit { 468 temperature = <95000>; /* millicelsius */ 469 hysteresis = <2000>; /* millicelsius */ 470 type = "critical"; 471 }; 472 }; 473 474 cooling-maps { 475 map0 { 476 trip = <&cpu_alert0>; 477 cooling-device = 478 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 479 }; 480 map1 { 481 trip = <&cpu_alert1>; 482 cooling-device = 483 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 484 }; 485 }; 486 }; 487 488 gpu { 489 polling-delay-passive = <100>; /* milliseconds */ 490 polling-delay = <5000>; /* milliseconds */ 491 492 thermal-sensors = <&tsadc 1>; 493 494 trips { 495 gpu_alert0: gpu_alert0 { 496 temperature = <80000>; /* millicelsius */ 497 hysteresis = <2000>; /* millicelsius */ 498 type = "passive"; 499 }; 500 gpu_crit: gpu_crit { 501 temperature = <115000>; /* millicelsius */ 502 hysteresis = <2000>; /* millicelsius */ 503 type = "critical"; 504 }; 505 }; 506 507 cooling-maps { 508 map0 { 509 trip = <&gpu_alert0>; 510 cooling-device = 511 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 512 }; 513 }; 514 }; 515 }; 516 517 tsadc: tsadc@ff280000 { 518 compatible = "rockchip,rk3368-tsadc"; 519 reg = <0x0 0xff280000 0x0 0x100>; 520 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 522 clock-names = "tsadc", "apb_pclk"; 523 resets = <&cru SRST_TSADC>; 524 reset-names = "tsadc-apb"; 525 pinctrl-names = "init", "default", "sleep"; 526 pinctrl-0 = <&otp_gpio>; 527 pinctrl-1 = <&otp_out>; 528 pinctrl-2 = <&otp_gpio>; 529 #thermal-sensor-cells = <1>; 530 rockchip,hw-tshut-temp = <95000>; 531 status = "disabled"; 532 }; 533 534 gmac: ethernet@ff290000 { 535 compatible = "rockchip,rk3368-gmac"; 536 reg = <0x0 0xff290000 0x0 0x10000>; 537 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 538 interrupt-names = "macirq"; 539 rockchip,grf = <&grf>; 540 clocks = <&cru SCLK_MAC>, 541 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 542 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 543 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 544 clock-names = "stmmaceth", 545 "mac_clk_rx", "mac_clk_tx", 546 "clk_mac_ref", "clk_mac_refout", 547 "aclk_mac", "pclk_mac"; 548 status = "disabled"; 549 }; 550 551 usb_host0_ehci: usb@ff500000 { 552 compatible = "generic-ehci"; 553 reg = <0x0 0xff500000 0x0 0x100>; 554 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cru HCLK_HOST0>; 556 clock-names = "usbhost"; 557 phys = <&u2phy_host>; 558 phy-names = "usb"; 559 status = "disabled"; 560 }; 561 562 usb_host0_ohci: usb@ff520000 { 563 compatible = "generic-ohci"; 564 reg = <0x0 0xff520000 0x0 0x20000>; 565 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&cru HCLK_HOST0>, <&u2phy>; 567 clock-names = "usbhost", "utmi"; 568 phys = <&u2phy_host>; 569 phy-names = "usb"; 570 status = "disabled"; 571 }; 572 573 usb_otg: usb@ff580000 { 574 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 575 "snps,dwc2"; 576 reg = <0x0 0xff580000 0x0 0x40000>; 577 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cru HCLK_OTG0>; 579 clock-names = "otg"; 580 dr_mode = "otg"; 581 g-np-tx-fifo-size = <16>; 582 g-rx-fifo-size = <275>; 583 g-tx-fifo-size = <256 128 128 64 64 32>; 584 g-use-dma; 585 phys = <&u2phy_otg>; 586 phy-names = "usb2-phy"; 587 status = "disabled"; 588 }; 589 590 i2c0: i2c@ff650000 { 591 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 592 reg = <0x0 0xff650000 0x0 0x1000>; 593 clocks = <&cru PCLK_I2C0>; 594 clock-names = "i2c"; 595 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&i2c0_xfer>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 i2c2: i2c@ff660000 { 604 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 605 reg = <0x0 0xff660000 0x0 0x1000>; 606 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 clock-names = "i2c"; 610 clocks = <&cru PCLK_I2C2>; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&i2c2_xfer>; 613 status = "disabled"; 614 }; 615 616 pwm0: pwm@ff680000 { 617 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 618 reg = <0x0 0xff680000 0x0 0x10>; 619 #pwm-cells = <3>; 620 pinctrl-names = "active"; 621 pinctrl-0 = <&pwm0_pin>; 622 clocks = <&cru PCLK_PWM1>; 623 clock-names = "pwm"; 624 status = "disabled"; 625 }; 626 627 pwm1: pwm@ff680010 { 628 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 629 reg = <0x0 0xff680010 0x0 0x10>; 630 #pwm-cells = <3>; 631 pinctrl-names = "active"; 632 pinctrl-0 = <&pwm1_pin>; 633 clocks = <&cru PCLK_PWM1>; 634 clock-names = "pwm"; 635 status = "disabled"; 636 }; 637 638 pwm2: pwm@ff680020 { 639 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 640 reg = <0x0 0xff680020 0x0 0x10>; 641 #pwm-cells = <3>; 642 clocks = <&cru PCLK_PWM1>; 643 clock-names = "pwm"; 644 status = "disabled"; 645 }; 646 647 pwm3: pwm@ff680030 { 648 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 649 reg = <0x0 0xff680030 0x0 0x10>; 650 #pwm-cells = <3>; 651 pinctrl-names = "active"; 652 pinctrl-0 = <&pwm3_pin>; 653 clocks = <&cru PCLK_PWM1>; 654 clock-names = "pwm"; 655 status = "disabled"; 656 }; 657 658 uart2: serial@ff690000 { 659 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 660 reg = <0x0 0xff690000 0x0 0x100>; 661 clock-frequency = <24000000>; 662 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 663 clock-names = "baudclk", "apb_pclk"; 664 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&uart2_xfer>; 667 reg-shift = <2>; 668 reg-io-width = <4>; 669 status = "disabled"; 670 }; 671 672 mbox: mbox@ff6b0000 { 673 compatible = "rockchip,rk3368-mailbox"; 674 reg = <0x0 0xff6b0000 0x0 0x1000>; 675 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&cru PCLK_MAILBOX>; 680 clock-names = "pclk_mailbox"; 681 #mbox-cells = <1>; 682 }; 683 684 pmugrf: syscon@ff738000 { 685 compatible = "rockchip,rk3368-pmugrf", "syscon"; 686 reg = <0x0 0xff738000 0x0 0x1000>; 687 }; 688 689 sgrf: syscon@ff740000 { 690 compatible = "rockchip,rk3368-sgrf", "syscon"; 691 reg = <0x0 0xff740000 0x0 0x1000>; 692 }; 693 694 cru: clock-controller@ff760000 { 695 compatible = "rockchip,rk3368-cru"; 696 reg = <0x0 0xff760000 0x0 0x1000>; 697 rockchip,grf = <&grf>; 698 #clock-cells = <1>; 699 #reset-cells = <1>; 700 }; 701 702 grf: syscon@ff770000 { 703 compatible = "rockchip,rk3368-grf", "syscon"; 704 reg = <0x0 0xff770000 0x0 0x1000>; 705 #address-cells = <1>; 706 #size-cells = <1>; 707 708 u2phy: usb2-phy@700 { 709 compatible = "rockchip,rk3368-usb2phy"; 710 reg = <0x700 0x2c>; 711 clocks = <&cru SCLK_OTGPHY0>; 712 clock-names = "phyclk"; 713 #clock-cells = <0>; 714 clock-output-names = "usbotg_out"; 715 assigned-clocks = <&cru SCLK_USBPHY480M>; 716 assigned-clock-parents = <&u2phy>; 717 status = "disabled"; 718 719 u2phy_otg: otg-port { 720 #phy-cells = <0>; 721 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 724 interrupt-names = "otg-bvalid", "otg-id", 725 "linestate"; 726 status = "disabled"; 727 }; 728 729 u2phy_host: host-port { 730 #phy-cells = <0>; 731 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 732 interrupt-names = "linestate"; 733 status = "disabled"; 734 }; 735 }; 736 }; 737 738 wdt: watchdog@ff800000 { 739 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 740 reg = <0x0 0xff800000 0x0 0x100>; 741 clocks = <&cru PCLK_WDT>; 742 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 743 status = "disabled"; 744 }; 745 746 timer0: timer@ff810000 { 747 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 748 reg = <0x0 0xff810000 0x0 0x20>; 749 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 750 }; 751 752 gic: interrupt-controller@ffb71000 { 753 compatible = "arm,gic-400"; 754 interrupt-controller; 755 #interrupt-cells = <3>; 756 #address-cells = <0>; 757 758 reg = <0x0 0xffb71000 0x0 0x1000>, 759 <0x0 0xffb72000 0x0 0x1000>, 760 <0x0 0xffb74000 0x0 0x2000>, 761 <0x0 0xffb76000 0x0 0x2000>; 762 interrupts = <GIC_PPI 9 763 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 764 }; 765 766 pinctrl: pinctrl { 767 compatible = "rockchip,rk3368-pinctrl"; 768 rockchip,grf = <&grf>; 769 rockchip,pmu = <&pmugrf>; 770 #address-cells = <0x2>; 771 #size-cells = <0x2>; 772 ranges; 773 774 gpio0: gpio0@ff750000 { 775 compatible = "rockchip,gpio-bank"; 776 reg = <0x0 0xff750000 0x0 0x100>; 777 clocks = <&cru PCLK_GPIO0>; 778 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 779 780 gpio-controller; 781 #gpio-cells = <0x2>; 782 783 interrupt-controller; 784 #interrupt-cells = <0x2>; 785 }; 786 787 gpio1: gpio1@ff780000 { 788 compatible = "rockchip,gpio-bank"; 789 reg = <0x0 0xff780000 0x0 0x100>; 790 clocks = <&cru PCLK_GPIO1>; 791 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 792 793 gpio-controller; 794 #gpio-cells = <0x2>; 795 796 interrupt-controller; 797 #interrupt-cells = <0x2>; 798 }; 799 800 gpio2: gpio2@ff790000 { 801 compatible = "rockchip,gpio-bank"; 802 reg = <0x0 0xff790000 0x0 0x100>; 803 clocks = <&cru PCLK_GPIO2>; 804 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 805 806 gpio-controller; 807 #gpio-cells = <0x2>; 808 809 interrupt-controller; 810 #interrupt-cells = <0x2>; 811 }; 812 813 gpio3: gpio3@ff7a0000 { 814 compatible = "rockchip,gpio-bank"; 815 reg = <0x0 0xff7a0000 0x0 0x100>; 816 clocks = <&cru PCLK_GPIO3>; 817 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 818 819 gpio-controller; 820 #gpio-cells = <0x2>; 821 822 interrupt-controller; 823 #interrupt-cells = <0x2>; 824 }; 825 826 pcfg_pull_up: pcfg-pull-up { 827 bias-pull-up; 828 }; 829 830 pcfg_pull_down: pcfg-pull-down { 831 bias-pull-down; 832 }; 833 834 pcfg_pull_none: pcfg-pull-none { 835 bias-disable; 836 }; 837 838 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 839 bias-disable; 840 drive-strength = <12>; 841 }; 842 843 emmc { 844 emmc_clk: emmc-clk { 845 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 846 }; 847 848 emmc_cmd: emmc-cmd { 849 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; 850 }; 851 852 emmc_pwr: emmc-pwr { 853 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; 854 }; 855 856 emmc_bus1: emmc-bus1 { 857 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; 858 }; 859 860 emmc_bus4: emmc-bus4 { 861 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 862 <1 19 RK_FUNC_2 &pcfg_pull_up>, 863 <1 20 RK_FUNC_2 &pcfg_pull_up>, 864 <1 21 RK_FUNC_2 &pcfg_pull_up>; 865 }; 866 867 emmc_bus8: emmc-bus8 { 868 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 869 <1 19 RK_FUNC_2 &pcfg_pull_up>, 870 <1 20 RK_FUNC_2 &pcfg_pull_up>, 871 <1 21 RK_FUNC_2 &pcfg_pull_up>, 872 <1 22 RK_FUNC_2 &pcfg_pull_up>, 873 <1 23 RK_FUNC_2 &pcfg_pull_up>, 874 <1 24 RK_FUNC_2 &pcfg_pull_up>, 875 <1 25 RK_FUNC_2 &pcfg_pull_up>; 876 }; 877 }; 878 879 gmac { 880 rgmii_pins: rgmii-pins { 881 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 882 <3 24 RK_FUNC_1 &pcfg_pull_none>, 883 <3 19 RK_FUNC_1 &pcfg_pull_none>, 884 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 885 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 886 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, 887 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, 888 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, 889 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 890 <3 15 RK_FUNC_1 &pcfg_pull_none>, 891 <3 16 RK_FUNC_1 &pcfg_pull_none>, 892 <3 17 RK_FUNC_1 &pcfg_pull_none>, 893 <3 18 RK_FUNC_1 &pcfg_pull_none>, 894 <3 25 RK_FUNC_1 &pcfg_pull_none>, 895 <3 20 RK_FUNC_1 &pcfg_pull_none>; 896 }; 897 898 rmii_pins: rmii-pins { 899 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 900 <3 24 RK_FUNC_1 &pcfg_pull_none>, 901 <3 19 RK_FUNC_1 &pcfg_pull_none>, 902 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 903 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 904 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 905 <3 15 RK_FUNC_1 &pcfg_pull_none>, 906 <3 16 RK_FUNC_1 &pcfg_pull_none>, 907 <3 20 RK_FUNC_1 &pcfg_pull_none>, 908 <3 21 RK_FUNC_1 &pcfg_pull_none>; 909 }; 910 }; 911 912 i2c0 { 913 i2c0_xfer: i2c0-xfer { 914 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 915 <0 7 RK_FUNC_1 &pcfg_pull_none>; 916 }; 917 }; 918 919 i2c1 { 920 i2c1_xfer: i2c1-xfer { 921 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, 922 <2 22 RK_FUNC_1 &pcfg_pull_none>; 923 }; 924 }; 925 926 i2c2 { 927 i2c2_xfer: i2c2-xfer { 928 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, 929 <3 31 RK_FUNC_2 &pcfg_pull_none>; 930 }; 931 }; 932 933 i2c3 { 934 i2c3_xfer: i2c3-xfer { 935 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, 936 <1 17 RK_FUNC_1 &pcfg_pull_none>; 937 }; 938 }; 939 940 i2c4 { 941 i2c4_xfer: i2c4-xfer { 942 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, 943 <3 25 RK_FUNC_2 &pcfg_pull_none>; 944 }; 945 }; 946 947 i2c5 { 948 i2c5_xfer: i2c5-xfer { 949 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, 950 <3 27 RK_FUNC_2 &pcfg_pull_none>; 951 }; 952 }; 953 954 pwm0 { 955 pwm0_pin: pwm0-pin { 956 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; 957 }; 958 }; 959 960 pwm1 { 961 pwm1_pin: pwm1-pin { 962 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; 963 }; 964 }; 965 966 pwm3 { 967 pwm3_pin: pwm3-pin { 968 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; 969 }; 970 }; 971 972 sdio0 { 973 sdio0_bus1: sdio0-bus1 { 974 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; 975 }; 976 977 sdio0_bus4: sdio0-bus4 { 978 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, 979 <2 29 RK_FUNC_1 &pcfg_pull_up>, 980 <2 30 RK_FUNC_1 &pcfg_pull_up>, 981 <2 31 RK_FUNC_1 &pcfg_pull_up>; 982 }; 983 984 sdio0_cmd: sdio0-cmd { 985 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; 986 }; 987 988 sdio0_clk: sdio0-clk { 989 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; 990 }; 991 992 sdio0_cd: sdio0-cd { 993 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; 994 }; 995 996 sdio0_wp: sdio0-wp { 997 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; 998 }; 999 1000 sdio0_pwr: sdio0-pwr { 1001 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; 1002 }; 1003 1004 sdio0_bkpwr: sdio0-bkpwr { 1005 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; 1006 }; 1007 1008 sdio0_int: sdio0-int { 1009 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; 1010 }; 1011 }; 1012 1013 sdmmc { 1014 sdmmc_clk: sdmmc-clk { 1015 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; 1016 }; 1017 1018 sdmmc_cmd: sdmmc-cmd { 1019 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; 1020 }; 1021 1022 sdmmc_cd: sdmmc-cd { 1023 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; 1024 }; 1025 1026 sdmmc_bus1: sdmmc-bus1 { 1027 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; 1028 }; 1029 1030 sdmmc_bus4: sdmmc-bus4 { 1031 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, 1032 <2 6 RK_FUNC_1 &pcfg_pull_up>, 1033 <2 7 RK_FUNC_1 &pcfg_pull_up>, 1034 <2 8 RK_FUNC_1 &pcfg_pull_up>; 1035 }; 1036 }; 1037 1038 spi0 { 1039 spi0_clk: spi0-clk { 1040 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; 1041 }; 1042 spi0_cs0: spi0-cs0 { 1043 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; 1044 }; 1045 spi0_cs1: spi0-cs1 { 1046 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; 1047 }; 1048 spi0_tx: spi0-tx { 1049 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; 1050 }; 1051 spi0_rx: spi0-rx { 1052 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; 1053 }; 1054 }; 1055 1056 spi1 { 1057 spi1_clk: spi1-clk { 1058 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; 1059 }; 1060 spi1_cs0: spi1-cs0 { 1061 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; 1062 }; 1063 spi1_cs1: spi1-cs1 { 1064 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; 1065 }; 1066 spi1_rx: spi1-rx { 1067 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; 1068 }; 1069 spi1_tx: spi1-tx { 1070 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; 1071 }; 1072 }; 1073 1074 spi2 { 1075 spi2_clk: spi2-clk { 1076 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; 1077 }; 1078 spi2_cs0: spi2-cs0 { 1079 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 1080 }; 1081 spi2_rx: spi2-rx { 1082 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; 1083 }; 1084 spi2_tx: spi2-tx { 1085 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 1086 }; 1087 }; 1088 1089 tsadc { 1090 otp_gpio: otp-gpio { 1091 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; 1092 }; 1093 1094 otp_out: otp-out { 1095 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>; 1096 }; 1097 }; 1098 1099 uart0 { 1100 uart0_xfer: uart0-xfer { 1101 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, 1102 <2 25 RK_FUNC_1 &pcfg_pull_none>; 1103 }; 1104 1105 uart0_cts: uart0-cts { 1106 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; 1107 }; 1108 1109 uart0_rts: uart0-rts { 1110 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; 1111 }; 1112 }; 1113 1114 uart1 { 1115 uart1_xfer: uart1-xfer { 1116 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, 1117 <0 21 RK_FUNC_3 &pcfg_pull_none>; 1118 }; 1119 1120 uart1_cts: uart1-cts { 1121 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; 1122 }; 1123 1124 uart1_rts: uart1-rts { 1125 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; 1126 }; 1127 }; 1128 1129 uart2 { 1130 uart2_xfer: uart2-xfer { 1131 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, 1132 <2 5 RK_FUNC_2 &pcfg_pull_none>; 1133 }; 1134 /* no rts / cts for uart2 */ 1135 }; 1136 1137 uart3 { 1138 uart3_xfer: uart3-xfer { 1139 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, 1140 <3 30 RK_FUNC_3 &pcfg_pull_none>; 1141 }; 1142 1143 uart3_cts: uart3-cts { 1144 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; 1145 }; 1146 1147 uart3_rts: uart3-rts { 1148 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; 1149 }; 1150 }; 1151 1152 uart4 { 1153 uart4_xfer: uart4-xfer { 1154 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, 1155 <0 26 RK_FUNC_3 &pcfg_pull_none>; 1156 }; 1157 1158 uart4_cts: uart4-cts { 1159 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; 1160 }; 1161 1162 uart4_rts: uart4-rts { 1163 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; 1164 }; 1165 }; 1166 }; 1167}; 1168