1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/rk3368-cru.h> 44#include <dt-bindings/gpio/gpio.h> 45#include <dt-bindings/interrupt-controller/irq.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/pinctrl/rockchip.h> 48#include <dt-bindings/thermal/thermal.h> 49#include <dt-bindings/memory/rk3368-dmc.h> 50 51/ { 52 compatible = "rockchip,rk3368"; 53 interrupt-parent = <&gic>; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 57 aliases { 58 ethernet0 = &gmac; 59 i2c0 = &i2c0; 60 i2c1 = &i2c1; 61 i2c2 = &i2c2; 62 i2c3 = &i2c3; 63 i2c4 = &i2c4; 64 i2c5 = &i2c5; 65 serial0 = &uart0; 66 serial1 = &uart1; 67 serial2 = &uart2; 68 serial3 = &uart3; 69 serial4 = &uart4; 70 spi0 = &spi0; 71 spi1 = &spi1; 72 spi2 = &spi2; 73 }; 74 75 cpus { 76 #address-cells = <0x2>; 77 #size-cells = <0x0>; 78 79 cpu-map { 80 cluster0 { 81 core0 { 82 cpu = <&cpu_b0>; 83 }; 84 core1 { 85 cpu = <&cpu_b1>; 86 }; 87 core2 { 88 cpu = <&cpu_b2>; 89 }; 90 core3 { 91 cpu = <&cpu_b3>; 92 }; 93 }; 94 95 cluster1 { 96 core0 { 97 cpu = <&cpu_l0>; 98 }; 99 core1 { 100 cpu = <&cpu_l1>; 101 }; 102 core2 { 103 cpu = <&cpu_l2>; 104 }; 105 core3 { 106 cpu = <&cpu_l3>; 107 }; 108 }; 109 }; 110 111 idle-states { 112 entry-method = "psci"; 113 114 cpu_sleep: cpu-sleep-0 { 115 compatible = "arm,idle-state"; 116 arm,psci-suspend-param = <0x1010000>; 117 entry-latency-us = <0x3fffffff>; 118 exit-latency-us = <0x40000000>; 119 min-residency-us = <0xffffffff>; 120 }; 121 }; 122 123 cpu_l0: cpu@0 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a53", "arm,armv8"; 126 reg = <0x0 0x0>; 127 cpu-idle-states = <&cpu_sleep>; 128 enable-method = "psci"; 129 130 #cooling-cells = <2>; /* min followed by max */ 131 }; 132 133 cpu_l1: cpu@1 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a53", "arm,armv8"; 136 reg = <0x0 0x1>; 137 cpu-idle-states = <&cpu_sleep>; 138 enable-method = "psci"; 139 }; 140 141 cpu_l2: cpu@2 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-a53", "arm,armv8"; 144 reg = <0x0 0x2>; 145 cpu-idle-states = <&cpu_sleep>; 146 enable-method = "psci"; 147 }; 148 149 cpu_l3: cpu@3 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a53", "arm,armv8"; 152 reg = <0x0 0x3>; 153 cpu-idle-states = <&cpu_sleep>; 154 enable-method = "psci"; 155 }; 156 157 cpu_b0: cpu@100 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a53", "arm,armv8"; 160 reg = <0x0 0x100>; 161 cpu-idle-states = <&cpu_sleep>; 162 enable-method = "psci"; 163 164 #cooling-cells = <2>; /* min followed by max */ 165 }; 166 167 cpu_b1: cpu@101 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a53", "arm,armv8"; 170 reg = <0x0 0x101>; 171 cpu-idle-states = <&cpu_sleep>; 172 enable-method = "psci"; 173 }; 174 175 cpu_b2: cpu@102 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a53", "arm,armv8"; 178 reg = <0x0 0x102>; 179 cpu-idle-states = <&cpu_sleep>; 180 enable-method = "psci"; 181 }; 182 183 cpu_b3: cpu@103 { 184 device_type = "cpu"; 185 compatible = "arm,cortex-a53", "arm,armv8"; 186 reg = <0x0 0x103>; 187 cpu-idle-states = <&cpu_sleep>; 188 enable-method = "psci"; 189 }; 190 }; 191 192 arm-pmu { 193 compatible = "arm,armv8-pmuv3"; 194 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 203 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 204 <&cpu_b2>, <&cpu_b3>; 205 }; 206 207 psci { 208 compatible = "arm,psci-0.2"; 209 method = "smc"; 210 }; 211 212 timer { 213 compatible = "arm,armv8-timer"; 214 interrupts = <GIC_PPI 13 215 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 216 <GIC_PPI 14 217 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 218 <GIC_PPI 11 219 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 220 <GIC_PPI 10 221 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 222 }; 223 224 xin24m: oscillator { 225 compatible = "fixed-clock"; 226 clock-frequency = <24000000>; 227 clock-output-names = "xin24m"; 228 #clock-cells = <0>; 229 }; 230 231 dmc: dmc@ff610000 { 232 compatible = "rockchip,rk3368-dmc", "syscon"; 233 rockchip,cru = <&cru>; 234 rockchip,grf = <&grf>; 235 rockchip,msch = <&service_msch>; 236 reg = <0 0xff610000 0 0x400 237 0 0xff620000 0 0x400>; 238 }; 239 240 service_msch: syscon@ffac0000 { 241 compatible = "rockchip,rk3368-msch", "syscon"; 242 reg = <0x0 0xffac0000 0x0 0x2000>; 243 status = "okay"; 244 }; 245 246 sdmmc: dwmmc@ff0c0000 { 247 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 248 reg = <0x0 0xff0c0000 0x0 0x4000>; 249 clock-freq-min-max = <400000 150000000>; 250 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 251 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 252 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 253 fifo-depth = <0x100>; 254 cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; 255 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 256 status = "disabled"; 257 }; 258 259 sdio0: dwmmc@ff0d0000 { 260 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 261 reg = <0x0 0xff0d0000 0x0 0x4000>; 262 clock-freq-min-max = <400000 150000000>; 263 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 264 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 265 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 266 fifo-depth = <0x100>; 267 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 268 status = "disabled"; 269 }; 270 271 emmc: dwmmc@ff0f0000 { 272 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 273 reg = <0x0 0xff0f0000 0x0 0x4000>; 274 clock-freq-min-max = <400000 150000000>; 275 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 276 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 277 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 278 fifo-depth = <0x100>; 279 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 280 status = "disabled"; 281 }; 282 283 saradc: saradc@ff100000 { 284 compatible = "rockchip,saradc"; 285 reg = <0x0 0xff100000 0x0 0x100>; 286 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 287 #io-channel-cells = <1>; 288 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 289 clock-names = "saradc", "apb_pclk"; 290 status = "disabled"; 291 }; 292 293 spi0: spi@ff110000 { 294 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 295 reg = <0x0 0xff110000 0x0 0x1000>; 296 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 297 clock-names = "spiclk", "apb_pclk"; 298 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 spi1: spi@ff120000 { 307 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 308 reg = <0x0 0xff120000 0x0 0x1000>; 309 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 310 clock-names = "spiclk", "apb_pclk"; 311 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 status = "disabled"; 317 }; 318 319 spi2: spi@ff130000 { 320 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 321 reg = <0x0 0xff130000 0x0 0x1000>; 322 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 323 clock-names = "spiclk", "apb_pclk"; 324 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 status = "disabled"; 330 }; 331 332 i2c1: i2c@ff140000 { 333 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 334 reg = <0x0 0xff140000 0x0 0x1000>; 335 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 clock-names = "i2c"; 339 clocks = <&cru PCLK_I2C1>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&i2c1_xfer>; 342 status = "disabled"; 343 }; 344 345 i2c3: i2c@ff150000 { 346 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 347 reg = <0x0 0xff150000 0x0 0x1000>; 348 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 clock-names = "i2c"; 352 clocks = <&cru PCLK_I2C3>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&i2c3_xfer>; 355 status = "disabled"; 356 }; 357 358 i2c4: i2c@ff160000 { 359 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 360 reg = <0x0 0xff160000 0x0 0x1000>; 361 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 clock-names = "i2c"; 365 clocks = <&cru PCLK_I2C4>; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&i2c4_xfer>; 368 status = "disabled"; 369 }; 370 371 i2c5: i2c@ff170000 { 372 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 373 reg = <0x0 0xff170000 0x0 0x1000>; 374 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 clock-names = "i2c"; 378 clocks = <&cru PCLK_I2C5>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&i2c5_xfer>; 381 status = "disabled"; 382 }; 383 384 nandc0: nandc@ff400000 { 385 compatible = "rockchip,rk-nandc"; 386 reg = <0x0 0xff400000 0x0 0x4000>; 387 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 388 nandc_id = <0>; 389 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>; 390 clock-names = "clk_nandc", "hclk_nandc"; 391 status = "disabled"; 392 }; 393 394 uart0: serial@ff180000 { 395 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 396 reg = <0x0 0xff180000 0x0 0x100>; 397 clock-frequency = <24000000>; 398 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 399 clock-names = "baudclk", "apb_pclk"; 400 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 401 reg-shift = <2>; 402 reg-io-width = <4>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&uart0_xfer>; 405 status = "disabled"; 406 }; 407 408 uart1: serial@ff190000 { 409 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 410 reg = <0x0 0xff190000 0x0 0x100>; 411 clock-frequency = <24000000>; 412 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 413 clock-names = "baudclk", "apb_pclk"; 414 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 415 reg-shift = <2>; 416 reg-io-width = <4>; 417 pinctrl-names = "default"; 418 pinctrl-1 = <&uart0_xfer>; 419 status = "disabled"; 420 }; 421 422 uart3: serial@ff1b0000 { 423 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 424 reg = <0x0 0xff1b0000 0x0 0x100>; 425 clock-frequency = <24000000>; 426 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 427 clock-names = "baudclk", "apb_pclk"; 428 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 429 reg-shift = <2>; 430 reg-io-width = <4>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&uart3_xfer>; 433 status = "disabled"; 434 }; 435 436 uart4: serial@ff1c0000 { 437 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 438 reg = <0x0 0xff1c0000 0x0 0x100>; 439 clock-frequency = <24000000>; 440 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 441 clock-names = "baudclk", "apb_pclk"; 442 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 443 reg-shift = <2>; 444 reg-io-width = <4>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&uart4_xfer>; 447 status = "disabled"; 448 }; 449 450 thermal-zones { 451 cpu { 452 polling-delay-passive = <100>; /* milliseconds */ 453 polling-delay = <5000>; /* milliseconds */ 454 455 thermal-sensors = <&tsadc 0>; 456 457 trips { 458 cpu_alert0: cpu_alert0 { 459 temperature = <75000>; /* millicelsius */ 460 hysteresis = <2000>; /* millicelsius */ 461 type = "passive"; 462 }; 463 cpu_alert1: cpu_alert1 { 464 temperature = <80000>; /* millicelsius */ 465 hysteresis = <2000>; /* millicelsius */ 466 type = "passive"; 467 }; 468 cpu_crit: cpu_crit { 469 temperature = <95000>; /* millicelsius */ 470 hysteresis = <2000>; /* millicelsius */ 471 type = "critical"; 472 }; 473 }; 474 475 cooling-maps { 476 map0 { 477 trip = <&cpu_alert0>; 478 cooling-device = 479 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 480 }; 481 map1 { 482 trip = <&cpu_alert1>; 483 cooling-device = 484 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 485 }; 486 }; 487 }; 488 489 gpu { 490 polling-delay-passive = <100>; /* milliseconds */ 491 polling-delay = <5000>; /* milliseconds */ 492 493 thermal-sensors = <&tsadc 1>; 494 495 trips { 496 gpu_alert0: gpu_alert0 { 497 temperature = <80000>; /* millicelsius */ 498 hysteresis = <2000>; /* millicelsius */ 499 type = "passive"; 500 }; 501 gpu_crit: gpu_crit { 502 temperature = <115000>; /* millicelsius */ 503 hysteresis = <2000>; /* millicelsius */ 504 type = "critical"; 505 }; 506 }; 507 508 cooling-maps { 509 map0 { 510 trip = <&gpu_alert0>; 511 cooling-device = 512 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 513 }; 514 }; 515 }; 516 }; 517 518 tsadc: tsadc@ff280000 { 519 compatible = "rockchip,rk3368-tsadc"; 520 reg = <0x0 0xff280000 0x0 0x100>; 521 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 523 clock-names = "tsadc", "apb_pclk"; 524 resets = <&cru SRST_TSADC>; 525 reset-names = "tsadc-apb"; 526 pinctrl-names = "init", "default", "sleep"; 527 pinctrl-0 = <&otp_gpio>; 528 pinctrl-1 = <&otp_out>; 529 pinctrl-2 = <&otp_gpio>; 530 #thermal-sensor-cells = <1>; 531 rockchip,hw-tshut-temp = <95000>; 532 status = "disabled"; 533 }; 534 535 gmac: ethernet@ff290000 { 536 compatible = "rockchip,rk3368-gmac"; 537 reg = <0x0 0xff290000 0x0 0x10000>; 538 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 539 interrupt-names = "macirq"; 540 rockchip,grf = <&grf>; 541 clocks = <&cru SCLK_MAC>, 542 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 543 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 544 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 545 clock-names = "stmmaceth", 546 "mac_clk_rx", "mac_clk_tx", 547 "clk_mac_ref", "clk_mac_refout", 548 "aclk_mac", "pclk_mac"; 549 status = "disabled"; 550 }; 551 552 usb_host0_ehci: usb@ff500000 { 553 compatible = "generic-ehci"; 554 reg = <0x0 0xff500000 0x0 0x100>; 555 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cru HCLK_HOST0>; 557 clock-names = "usbhost"; 558 phys = <&u2phy_host>; 559 phy-names = "usb"; 560 status = "disabled"; 561 }; 562 563 usb_host0_ohci: usb@ff520000 { 564 compatible = "generic-ohci"; 565 reg = <0x0 0xff520000 0x0 0x20000>; 566 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&cru HCLK_HOST0>, <&u2phy>; 568 clock-names = "usbhost", "utmi"; 569 phys = <&u2phy_host>; 570 phy-names = "usb"; 571 status = "disabled"; 572 }; 573 574 usb_otg: usb@ff580000 { 575 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 576 "snps,dwc2"; 577 reg = <0x0 0xff580000 0x0 0x40000>; 578 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&cru HCLK_OTG0>; 580 clock-names = "otg"; 581 dr_mode = "otg"; 582 g-np-tx-fifo-size = <16>; 583 g-rx-fifo-size = <275>; 584 g-tx-fifo-size = <256 128 128 64 64 32>; 585 g-use-dma; 586 phys = <&u2phy_otg>; 587 phy-names = "usb2-phy"; 588 status = "disabled"; 589 }; 590 591 i2c0: i2c@ff650000 { 592 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 593 reg = <0x0 0xff650000 0x0 0x1000>; 594 clocks = <&cru PCLK_I2C0>; 595 clock-names = "i2c"; 596 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&i2c0_xfer>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 i2c2: i2c@ff660000 { 605 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 606 reg = <0x0 0xff660000 0x0 0x1000>; 607 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 clock-names = "i2c"; 611 clocks = <&cru PCLK_I2C2>; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&i2c2_xfer>; 614 status = "disabled"; 615 }; 616 617 pwm0: pwm@ff680000 { 618 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 619 reg = <0x0 0xff680000 0x0 0x10>; 620 #pwm-cells = <3>; 621 pinctrl-names = "active"; 622 pinctrl-0 = <&pwm0_pin>; 623 clocks = <&cru PCLK_PWM1>; 624 clock-names = "pwm"; 625 status = "disabled"; 626 }; 627 628 pwm1: pwm@ff680010 { 629 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 630 reg = <0x0 0xff680010 0x0 0x10>; 631 #pwm-cells = <3>; 632 pinctrl-names = "active"; 633 pinctrl-0 = <&pwm1_pin>; 634 clocks = <&cru PCLK_PWM1>; 635 clock-names = "pwm"; 636 status = "disabled"; 637 }; 638 639 pwm2: pwm@ff680020 { 640 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 641 reg = <0x0 0xff680020 0x0 0x10>; 642 #pwm-cells = <3>; 643 clocks = <&cru PCLK_PWM1>; 644 clock-names = "pwm"; 645 status = "disabled"; 646 }; 647 648 pwm3: pwm@ff680030 { 649 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 650 reg = <0x0 0xff680030 0x0 0x10>; 651 #pwm-cells = <3>; 652 pinctrl-names = "active"; 653 pinctrl-0 = <&pwm3_pin>; 654 clocks = <&cru PCLK_PWM1>; 655 clock-names = "pwm"; 656 status = "disabled"; 657 }; 658 659 uart2: serial@ff690000 { 660 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 661 reg = <0x0 0xff690000 0x0 0x100>; 662 clock-frequency = <24000000>; 663 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 664 clock-names = "baudclk", "apb_pclk"; 665 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&uart2_xfer>; 668 reg-shift = <2>; 669 reg-io-width = <4>; 670 status = "disabled"; 671 }; 672 673 mbox: mbox@ff6b0000 { 674 compatible = "rockchip,rk3368-mailbox"; 675 reg = <0x0 0xff6b0000 0x0 0x1000>; 676 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cru PCLK_MAILBOX>; 681 clock-names = "pclk_mailbox"; 682 #mbox-cells = <1>; 683 }; 684 685 pmugrf: syscon@ff738000 { 686 compatible = "rockchip,rk3368-pmugrf", "syscon"; 687 reg = <0x0 0xff738000 0x0 0x1000>; 688 }; 689 690 sgrf: syscon@ff740000 { 691 compatible = "rockchip,rk3368-sgrf", "syscon"; 692 reg = <0x0 0xff740000 0x0 0x1000>; 693 }; 694 695 cru: clock-controller@ff760000 { 696 compatible = "rockchip,rk3368-cru"; 697 reg = <0x0 0xff760000 0x0 0x1000>; 698 rockchip,grf = <&grf>; 699 #clock-cells = <1>; 700 #reset-cells = <1>; 701 }; 702 703 grf: syscon@ff770000 { 704 compatible = "rockchip,rk3368-grf", "syscon"; 705 reg = <0x0 0xff770000 0x0 0x1000>; 706 #address-cells = <1>; 707 #size-cells = <1>; 708 709 u2phy: usb2-phy@700 { 710 compatible = "rockchip,rk3368-usb2phy"; 711 reg = <0x700 0x2c>; 712 clocks = <&cru SCLK_OTGPHY0>; 713 clock-names = "phyclk"; 714 #clock-cells = <0>; 715 clock-output-names = "usbotg_out"; 716 assigned-clocks = <&cru SCLK_USBPHY480M>; 717 assigned-clock-parents = <&u2phy>; 718 status = "disabled"; 719 720 u2phy_otg: otg-port { 721 #phy-cells = <0>; 722 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 725 interrupt-names = "otg-bvalid", "otg-id", 726 "linestate"; 727 status = "disabled"; 728 }; 729 730 u2phy_host: host-port { 731 #phy-cells = <0>; 732 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 733 interrupt-names = "linestate"; 734 status = "disabled"; 735 }; 736 }; 737 }; 738 739 wdt: watchdog@ff800000 { 740 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 741 reg = <0x0 0xff800000 0x0 0x100>; 742 clocks = <&cru PCLK_WDT>; 743 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 744 status = "disabled"; 745 }; 746 747 timer0: timer@ff810000 { 748 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 749 reg = <0x0 0xff810000 0x0 0x20>; 750 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 751 }; 752 753 gic: interrupt-controller@ffb71000 { 754 compatible = "arm,gic-400"; 755 interrupt-controller; 756 #interrupt-cells = <3>; 757 #address-cells = <0>; 758 759 reg = <0x0 0xffb71000 0x0 0x1000>, 760 <0x0 0xffb72000 0x0 0x1000>, 761 <0x0 0xffb74000 0x0 0x2000>, 762 <0x0 0xffb76000 0x0 0x2000>; 763 interrupts = <GIC_PPI 9 764 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 765 }; 766 767 pinctrl: pinctrl { 768 compatible = "rockchip,rk3368-pinctrl"; 769 rockchip,grf = <&grf>; 770 rockchip,pmu = <&pmugrf>; 771 #address-cells = <0x2>; 772 #size-cells = <0x2>; 773 ranges; 774 775 gpio0: gpio0@ff750000 { 776 compatible = "rockchip,gpio-bank"; 777 reg = <0x0 0xff750000 0x0 0x100>; 778 clocks = <&cru PCLK_GPIO0>; 779 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 780 781 gpio-controller; 782 #gpio-cells = <0x2>; 783 784 interrupt-controller; 785 #interrupt-cells = <0x2>; 786 }; 787 788 gpio1: gpio1@ff780000 { 789 compatible = "rockchip,gpio-bank"; 790 reg = <0x0 0xff780000 0x0 0x100>; 791 clocks = <&cru PCLK_GPIO1>; 792 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 793 794 gpio-controller; 795 #gpio-cells = <0x2>; 796 797 interrupt-controller; 798 #interrupt-cells = <0x2>; 799 }; 800 801 gpio2: gpio2@ff790000 { 802 compatible = "rockchip,gpio-bank"; 803 reg = <0x0 0xff790000 0x0 0x100>; 804 clocks = <&cru PCLK_GPIO2>; 805 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 806 807 gpio-controller; 808 #gpio-cells = <0x2>; 809 810 interrupt-controller; 811 #interrupt-cells = <0x2>; 812 }; 813 814 gpio3: gpio3@ff7a0000 { 815 compatible = "rockchip,gpio-bank"; 816 reg = <0x0 0xff7a0000 0x0 0x100>; 817 clocks = <&cru PCLK_GPIO3>; 818 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 819 820 gpio-controller; 821 #gpio-cells = <0x2>; 822 823 interrupt-controller; 824 #interrupt-cells = <0x2>; 825 }; 826 827 pcfg_pull_up: pcfg-pull-up { 828 bias-pull-up; 829 }; 830 831 pcfg_pull_down: pcfg-pull-down { 832 bias-pull-down; 833 }; 834 835 pcfg_pull_none: pcfg-pull-none { 836 bias-disable; 837 }; 838 839 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 840 bias-disable; 841 drive-strength = <12>; 842 }; 843 844 emmc { 845 emmc_clk: emmc-clk { 846 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; 847 }; 848 849 emmc_cmd: emmc-cmd { 850 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>; 851 }; 852 853 emmc_pwr: emmc-pwr { 854 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>; 855 }; 856 857 emmc_bus1: emmc-bus1 { 858 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>; 859 }; 860 861 emmc_bus4: emmc-bus4 { 862 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 863 <1 19 RK_FUNC_2 &pcfg_pull_up>, 864 <1 20 RK_FUNC_2 &pcfg_pull_up>, 865 <1 21 RK_FUNC_2 &pcfg_pull_up>; 866 }; 867 868 emmc_bus8: emmc-bus8 { 869 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>, 870 <1 19 RK_FUNC_2 &pcfg_pull_up>, 871 <1 20 RK_FUNC_2 &pcfg_pull_up>, 872 <1 21 RK_FUNC_2 &pcfg_pull_up>, 873 <1 22 RK_FUNC_2 &pcfg_pull_up>, 874 <1 23 RK_FUNC_2 &pcfg_pull_up>, 875 <1 24 RK_FUNC_2 &pcfg_pull_up>, 876 <1 25 RK_FUNC_2 &pcfg_pull_up>; 877 }; 878 }; 879 880 gmac { 881 rgmii_pins: rgmii-pins { 882 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 883 <3 24 RK_FUNC_1 &pcfg_pull_none>, 884 <3 19 RK_FUNC_1 &pcfg_pull_none>, 885 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 886 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 887 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>, 888 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>, 889 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>, 890 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 891 <3 15 RK_FUNC_1 &pcfg_pull_none>, 892 <3 16 RK_FUNC_1 &pcfg_pull_none>, 893 <3 17 RK_FUNC_1 &pcfg_pull_none>, 894 <3 18 RK_FUNC_1 &pcfg_pull_none>, 895 <3 25 RK_FUNC_1 &pcfg_pull_none>, 896 <3 20 RK_FUNC_1 &pcfg_pull_none>; 897 }; 898 899 rmii_pins: rmii-pins { 900 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>, 901 <3 24 RK_FUNC_1 &pcfg_pull_none>, 902 <3 19 RK_FUNC_1 &pcfg_pull_none>, 903 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>, 904 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>, 905 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>, 906 <3 15 RK_FUNC_1 &pcfg_pull_none>, 907 <3 16 RK_FUNC_1 &pcfg_pull_none>, 908 <3 20 RK_FUNC_1 &pcfg_pull_none>, 909 <3 21 RK_FUNC_1 &pcfg_pull_none>; 910 }; 911 }; 912 913 i2c0 { 914 i2c0_xfer: i2c0-xfer { 915 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, 916 <0 7 RK_FUNC_1 &pcfg_pull_none>; 917 }; 918 }; 919 920 i2c1 { 921 i2c1_xfer: i2c1-xfer { 922 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>, 923 <2 22 RK_FUNC_1 &pcfg_pull_none>; 924 }; 925 }; 926 927 i2c2 { 928 i2c2_xfer: i2c2-xfer { 929 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>, 930 <3 31 RK_FUNC_2 &pcfg_pull_none>; 931 }; 932 }; 933 934 i2c3 { 935 i2c3_xfer: i2c3-xfer { 936 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>, 937 <1 17 RK_FUNC_1 &pcfg_pull_none>; 938 }; 939 }; 940 941 i2c4 { 942 i2c4_xfer: i2c4-xfer { 943 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>, 944 <3 25 RK_FUNC_2 &pcfg_pull_none>; 945 }; 946 }; 947 948 i2c5 { 949 i2c5_xfer: i2c5-xfer { 950 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>, 951 <3 27 RK_FUNC_2 &pcfg_pull_none>; 952 }; 953 }; 954 955 pwm0 { 956 pwm0_pin: pwm0-pin { 957 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; 958 }; 959 }; 960 961 pwm1 { 962 pwm1_pin: pwm1-pin { 963 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; 964 }; 965 }; 966 967 pwm3 { 968 pwm3_pin: pwm3-pin { 969 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; 970 }; 971 }; 972 973 sdio0 { 974 sdio0_bus1: sdio0-bus1 { 975 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; 976 }; 977 978 sdio0_bus4: sdio0-bus4 { 979 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>, 980 <2 29 RK_FUNC_1 &pcfg_pull_up>, 981 <2 30 RK_FUNC_1 &pcfg_pull_up>, 982 <2 31 RK_FUNC_1 &pcfg_pull_up>; 983 }; 984 985 sdio0_cmd: sdio0-cmd { 986 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>; 987 }; 988 989 sdio0_clk: sdio0-clk { 990 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>; 991 }; 992 993 sdio0_cd: sdio0-cd { 994 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>; 995 }; 996 997 sdio0_wp: sdio0-wp { 998 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>; 999 }; 1000 1001 sdio0_pwr: sdio0-pwr { 1002 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>; 1003 }; 1004 1005 sdio0_bkpwr: sdio0-bkpwr { 1006 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>; 1007 }; 1008 1009 sdio0_int: sdio0-int { 1010 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>; 1011 }; 1012 }; 1013 1014 sdmmc { 1015 sdmmc_clk: sdmmc-clk { 1016 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>; 1017 }; 1018 1019 sdmmc_cmd: sdmmc-cmd { 1020 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; 1021 }; 1022 1023 sdmmc_cd: sdmmc-cd { 1024 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; 1025 }; 1026 1027 sdmmc_bus1: sdmmc-bus1 { 1028 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>; 1029 }; 1030 1031 sdmmc_bus4: sdmmc-bus4 { 1032 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>, 1033 <2 6 RK_FUNC_1 &pcfg_pull_up>, 1034 <2 7 RK_FUNC_1 &pcfg_pull_up>, 1035 <2 8 RK_FUNC_1 &pcfg_pull_up>; 1036 }; 1037 }; 1038 1039 spi0 { 1040 spi0_clk: spi0-clk { 1041 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>; 1042 }; 1043 spi0_cs0: spi0-cs0 { 1044 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>; 1045 }; 1046 spi0_cs1: spi0-cs1 { 1047 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>; 1048 }; 1049 spi0_tx: spi0-tx { 1050 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>; 1051 }; 1052 spi0_rx: spi0-rx { 1053 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>; 1054 }; 1055 }; 1056 1057 spi1 { 1058 spi1_clk: spi1-clk { 1059 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>; 1060 }; 1061 spi1_cs0: spi1-cs0 { 1062 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>; 1063 }; 1064 spi1_cs1: spi1-cs1 { 1065 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>; 1066 }; 1067 spi1_rx: spi1-rx { 1068 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>; 1069 }; 1070 spi1_tx: spi1-tx { 1071 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>; 1072 }; 1073 }; 1074 1075 spi2 { 1076 spi2_clk: spi2-clk { 1077 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>; 1078 }; 1079 spi2_cs0: spi2-cs0 { 1080 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>; 1081 }; 1082 spi2_rx: spi2-rx { 1083 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>; 1084 }; 1085 spi2_tx: spi2-tx { 1086 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>; 1087 }; 1088 }; 1089 1090 tsadc { 1091 otp_gpio: otp-gpio { 1092 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; 1093 }; 1094 1095 otp_out: otp-out { 1096 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>; 1097 }; 1098 }; 1099 1100 uart0 { 1101 uart0_xfer: uart0-xfer { 1102 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>, 1103 <2 25 RK_FUNC_1 &pcfg_pull_none>; 1104 }; 1105 1106 uart0_cts: uart0-cts { 1107 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>; 1108 }; 1109 1110 uart0_rts: uart0-rts { 1111 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>; 1112 }; 1113 }; 1114 1115 uart1 { 1116 uart1_xfer: uart1-xfer { 1117 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>, 1118 <0 21 RK_FUNC_3 &pcfg_pull_none>; 1119 }; 1120 1121 uart1_cts: uart1-cts { 1122 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>; 1123 }; 1124 1125 uart1_rts: uart1-rts { 1126 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>; 1127 }; 1128 }; 1129 1130 uart2 { 1131 uart2_xfer: uart2-xfer { 1132 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>, 1133 <2 5 RK_FUNC_2 &pcfg_pull_none>; 1134 }; 1135 /* no rts / cts for uart2 */ 1136 }; 1137 1138 uart3 { 1139 uart3_xfer: uart3-xfer { 1140 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>, 1141 <3 30 RK_FUNC_3 &pcfg_pull_none>; 1142 }; 1143 1144 uart3_cts: uart3-cts { 1145 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>; 1146 }; 1147 1148 uart3_rts: uart3-rts { 1149 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>; 1150 }; 1151 }; 1152 1153 uart4 { 1154 uart4_xfer: uart4-xfer { 1155 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>, 1156 <0 26 RK_FUNC_3 &pcfg_pull_none>; 1157 }; 1158 1159 uart4_cts: uart4-cts { 1160 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>; 1161 }; 1162 1163 uart4_rts: uart4-rts { 1164 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>; 1165 }; 1166 }; 1167 }; 1168}; 1169