1/* 2 * Google Veyron (and derivatives) board device tree source 3 * 4 * Copyright 2014 Google, Inc 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9#include <dt-bindings/clock/rockchip,rk808.h> 10#include <dt-bindings/input/input.h> 11#include "rk3288.dtsi" 12 13/ { 14 memory { 15 reg = <0x0 0x80000000>; 16 }; 17 18 chosen { 19 stdout-path = &uart2; 20 u-boot,spl-boot-order = &spi_flash; 21 }; 22 23 firmware { 24 chromeos { 25 pinctrl-names = "default"; 26 pinctrl-0 = <&fw_wp_ap>; 27 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>; 28 }; 29 }; 30 31 backlight: backlight { 32 compatible = "pwm-backlight"; 33 brightness-levels = < 34 0 1 2 3 4 5 6 7 35 8 9 10 11 12 13 14 15 36 16 17 18 19 20 21 22 23 37 24 25 26 27 28 29 30 31 38 32 33 34 35 36 37 38 39 39 40 41 42 43 44 45 46 47 40 48 49 50 51 52 53 54 55 41 56 57 58 59 60 61 62 63 42 64 65 66 67 68 69 70 71 43 72 73 74 75 76 77 78 79 44 80 81 82 83 84 85 86 87 45 88 89 90 91 92 93 94 95 46 96 97 98 99 100 101 102 103 47 104 105 106 107 108 109 110 111 48 112 113 114 115 116 117 118 119 49 120 121 122 123 124 125 126 127 50 128 129 130 131 132 133 134 135 51 136 137 138 139 140 141 142 143 52 144 145 146 147 148 149 150 151 53 152 153 154 155 156 157 158 159 54 160 161 162 163 164 165 166 167 55 168 169 170 171 172 173 174 175 56 176 177 178 179 180 181 182 183 57 184 185 186 187 188 189 190 191 58 192 193 194 195 196 197 198 199 59 200 201 202 203 204 205 206 207 60 208 209 210 211 212 213 214 215 61 216 217 218 219 220 221 222 223 62 224 225 226 227 228 229 230 231 63 232 233 234 235 236 237 238 239 64 240 241 242 243 244 245 246 247 65 248 249 250 251 252 253 254 255>; 66 default-brightness-level = <128>; 67 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 68 backlight-boot-off; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&bl_en>; 71 pwms = <&pwm0 0 1000000 0>; 72 }; 73 74 panel: panel { 75 compatible ="cnm,n116bgeea2","simple-panel"; 76 status = "okay"; 77 power-supply = <&vcc33_lcd>; 78 backlight = <&backlight>; 79 }; 80 81 gpio_keys: gpio-keys { 82 compatible = "gpio-keys"; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pwr_key_h>; 88 power { 89 label = "Power"; 90 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; 91 linux,code = <KEY_POWER>; 92 debounce-interval = <100>; 93 gpio-key,wakeup; 94 }; 95 }; 96 97 gpio-restart { 98 compatible = "gpio-restart"; 99 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&ap_warm_reset_h>; 102 priority = /bits/ 8 <200>; 103 }; 104 105 emmc_pwrseq: emmc-pwrseq { 106 compatible = "mmc-pwrseq-emmc"; 107 pinctrl-0 = <&emmc_reset>; 108 pinctrl-names = "default"; 109 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; 110 }; 111 112 sound { 113 compatible = "rockchip,rockchip-audio-max98090"; 114 rockchip,model = "ROCKCHIP-I2S"; 115 rockchip,i2s-controller = <&i2s>; 116 rockchip,audio-codec = <&max98090>; 117 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; 118 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 119 rockchip,headset-codec = <&headsetcodec>; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&mic_det>, <&hp_det>; 122 }; 123 124 vdd_logic: pwm-regulator { 125 compatible = "pwm-regulator"; 126 pwms = <&pwm1 0 2000 0>; 127 128 voltage-table = <1350000 0>, 129 <1300000 10>, 130 <1250000 20>, 131 <1200000 31>, 132 <1150000 41>, 133 <1100000 52>, 134 <1050000 62>, 135 <1000000 72>, 136 < 950000 83>; 137 138 regulator-min-microvolt = <950000>; 139 regulator-max-microvolt = <1350000>; 140 regulator-name = "vdd_logic"; 141 regulator-ramp-delay = <4000>; 142 }; 143 144 vcc33_sys: vcc33-sys { 145 compatible = "regulator-fixed"; 146 regulator-name = "vcc33_sys"; 147 regulator-always-on; 148 regulator-boot-on; 149 regulator-min-microvolt = <3300000>; 150 regulator-max-microvolt = <3300000>; 151 vin-supply = <&vccsys>; 152 }; 153 154 vcc_5v: vcc-5v { 155 compatible = "regulator-fixed"; 156 regulator-name = "vcc_5v"; 157 regulator-always-on; 158 regulator-boot-on; 159 regulator-min-microvolt = <5000000>; 160 regulator-max-microvolt = <5000000>; 161 }; 162 163 vcc50_hdmi: vcc50-hdmi { 164 compatible = "regulator-fixed"; 165 regulator-name = "vcc50_hdmi"; 166 regulator-always-on; 167 regulator-boot-on; 168 vin-supply = <&vcc_5v>; 169 }; 170 171 bt_regulator: bt-regulator { 172 /* 173 * On the module itself this is one of these (depending 174 * on the actual card pouplated): 175 * - BT_I2S_WS_BT_RFDISABLE_L 176 * - No connect 177 */ 178 179 compatible = "regulator-fixed"; 180 enable-active-high; 181 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&bt_enable_l>; 184 regulator-name = "bt_regulator"; 185 }; 186 187 wifi_regulator: wifi-regulator { 188 /* 189 * On the module itself this is one of these (depending 190 * on the actual card populated): 191 * - SDIO_RESET_L_WL_REG_ON 192 * - PDN (power down when low) 193 */ 194 195 compatible = "regulator-fixed"; 196 enable-active-high; 197 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&wifi_enable_h>; 200 regulator-name = "wifi_regulator"; 201 202 /* Faux input supply. See bt_regulator description. */ 203 vin-supply = <&bt_regulator>; 204 }; 205 206 io-domains { 207 compatible = "rockchip,rk3288-io-voltage-domain"; 208 rockchip,grf = <&grf>; 209 210 audio-supply = <&vcc18_codec>; 211 bb-supply = <&vcc33_io>; 212 dvp-supply = <&vcc_18>; 213 flash0-supply = <&vcc18_flashio>; 214 gpio1830-supply = <&vcc33_io>; 215 gpio30-supply = <&vcc33_io>; 216 lcdc-supply = <&vcc33_lcd>; 217 sdcard-supply = <&vccio_sd>; 218 wifi-supply = <&vcc18_wl>; 219 }; 220}; 221 222&cpu0 { 223 cpu0-supply = <&vdd_cpu>; 224}; 225 226&dmc { 227 logic-supply = <&vdd_logic>; 228 rockchip,odt-disable-freq = <333000000>; 229 rockchip,dll-disable-freq = <333000000>; 230 rockchip,sr-enable-freq = <333000000>; 231 rockchip,pd-enable-freq = <666000000>; 232 rockchip,auto-self-refresh-cnt = <0>; 233 rockchip,auto-power-down-cnt = <64>; 234 rockchip,ddr-speed-bin = <21>; 235 rockchip,trcd = <10>; 236 rockchip,trp = <10>; 237 operating-points = < 238 /* KHz uV */ 239 200000 1050000 240 333000 1100000 241 533000 1150000 242 666000 1200000 243 >; 244}; 245 246&efuse { 247 status = "okay"; 248}; 249 250&emmc { 251 broken-cd; 252 bus-width = <8>; 253 cap-mmc-highspeed; 254 mmc-hs200-1_8v; 255 mmc-pwrseq = <&emmc_pwrseq>; 256 disable-wp; 257 non-removable; 258 num-slots = <1>; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>; 261 status = "okay"; 262}; 263 264&sdio0 { 265 broken-cd; 266 bus-width = <4>; 267 cap-sd-highspeed; 268 sd-uhs-sdr12; 269 sd-uhs-sdr25; 270 sd-uhs-sdr50; 271 sd-uhs-sdr104; 272 cap-sdio-irq; 273 card-external-vcc-supply = <&wifi_regulator>; 274 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, 275 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>; 276 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock"; 277 keep-power-in-suspend; 278 non-removable; 279 num-slots = <1>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; 282 status = "okay"; 283 vmmc-supply = <&vcc33_sys>; 284 vqmmc-supply = <&vcc18_wl>; 285}; 286 287&sdmmc { 288 bus-width = <4>; 289 cap-mmc-highspeed; 290 cap-sd-highspeed; 291 sd-uhs-sdr12; 292 sd-uhs-sdr25; 293 sd-uhs-sdr50; 294 sd-uhs-sdr104; 295 card-detect-delay = <200>; 296 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; 297 num-slots = <1>; 298 status = "okay"; 299 vmmc-supply = <&vcc33_sd>; 300 vqmmc-supply = <&vccio_sd>; 301}; 302 303&spi2 { 304 status = "okay"; 305 u-boot,dm-pre-reloc; 306 307 spi_flash: spiflash@0 { 308 u-boot,dm-pre-reloc; 309 compatible = "spidev", "spi-flash"; 310 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ 311 reg = <0>; 312 }; 313}; 314 315&i2c0 { 316 status = "okay"; 317 318 clock-frequency = <400000>; 319 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ 320 i2c-scl-rising-time-ns = <100>; /* 45ns measured */ 321 u-boot,dm-pre-reloc; 322 323 rk808: pmic@1b { 324 compatible = "rockchip,rk808"; 325 clock-output-names = "xin32k", "wifibt_32kin"; 326 interrupt-parent = <&gpio0>; 327 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pmic_int_l>; 330 reg = <0x1b>; 331 rockchip,system-power-controller; 332 wakeup-source; 333 #clock-cells = <1>; 334 u-boot,dm-pre-reloc; 335 336 vcc1-supply = <&vcc33_sys>; 337 vcc2-supply = <&vcc33_sys>; 338 vcc3-supply = <&vcc33_sys>; 339 vcc4-supply = <&vcc33_sys>; 340 vcc6-supply = <&vcc_5v>; 341 vcc7-supply = <&vcc33_sys>; 342 vcc8-supply = <&vcc33_sys>; 343 vcc9-supply = <&vcc_5v>; 344 vcc10-supply = <&vcc33_sys>; 345 vcc11-supply = <&vcc_5v>; 346 vcc12-supply = <&vcc_18>; 347 348 vddio-supply = <&vcc33_io>; 349 350 regulators { 351 vdd_cpu: DCDC_REG1 { 352 regulator-always-on; 353 regulator-boot-on; 354 regulator-min-microvolt = <750000>; 355 regulator-max-microvolt = <1450000>; 356 regulator-name = "vdd_arm"; 357 regulator-ramp-delay = <6001>; 358 regulator-suspend-mem-disabled; 359 }; 360 361 vdd_gpu: DCDC_REG2 { 362 regulator-always-on; 363 regulator-boot-on; 364 regulator-min-microvolt = <800000>; 365 regulator-max-microvolt = <1250000>; 366 regulator-name = "vdd_gpu"; 367 regulator-ramp-delay = <6001>; 368 regulator-suspend-mem-disabled; 369 }; 370 371 vcc135_ddr: DCDC_REG3 { 372 regulator-always-on; 373 regulator-boot-on; 374 regulator-name = "vcc135_ddr"; 375 regulator-suspend-mem-enabled; 376 }; 377 378 /* 379 * vcc_18 has several aliases. (vcc18_flashio and 380 * vcc18_wl). We'll add those aliases here just to 381 * make it easier to follow the schematic. The signals 382 * are actually hooked together and only separated for 383 * power measurement purposes). 384 */ 385 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { 386 regulator-always-on; 387 regulator-boot-on; 388 regulator-min-microvolt = <1800000>; 389 regulator-max-microvolt = <1800000>; 390 regulator-name = "vcc_18"; 391 regulator-suspend-mem-microvolt = <1800000>; 392 }; 393 394 /* 395 * Note that both vcc33_io and vcc33_pmuio are always 396 * powered together. To simplify the logic in the dts 397 * we just refer to vcc33_io every time something is 398 * powered from vcc33_pmuio. In fact, on later boards 399 * (such as danger) they're the same net. 400 */ 401 vcc33_io: LDO_REG1 { 402 regulator-always-on; 403 regulator-boot-on; 404 regulator-min-microvolt = <3300000>; 405 regulator-max-microvolt = <3300000>; 406 regulator-name = "vcc33_io"; 407 regulator-suspend-mem-microvolt = <3300000>; 408 }; 409 410 vdd_10: LDO_REG3 { 411 regulator-always-on; 412 regulator-boot-on; 413 regulator-min-microvolt = <1000000>; 414 regulator-max-microvolt = <1000000>; 415 regulator-name = "vdd_10"; 416 regulator-suspend-mem-microvolt = <1000000>; 417 }; 418 419 vccio_sd: LDO_REG4 { 420 regulator-min-microvolt = <1800000>; 421 regulator-max-microvolt = <3300000>; 422 regulator-name = "vccio_sd"; 423 regulator-suspend-mem-disabled; 424 }; 425 426 vcc33_sd: LDO_REG5 { 427 regulator-min-microvolt = <3300000>; 428 regulator-max-microvolt = <3300000>; 429 regulator-name = "vcc33_sd"; 430 regulator-suspend-mem-disabled; 431 }; 432 433 vcc18_codec: LDO_REG6 { 434 regulator-always-on; 435 regulator-boot-on; 436 regulator-min-microvolt = <1800000>; 437 regulator-max-microvolt = <1800000>; 438 regulator-name = "vcc18_codec"; 439 regulator-suspend-mem-disabled; 440 }; 441 442 vdd10_lcd_pwren_h: LDO_REG7 { 443 regulator-always-on; 444 regulator-boot-on; 445 regulator-min-microvolt = <2500000>; 446 regulator-max-microvolt = <2500000>; 447 regulator-name = "vdd10_lcd_pwren_h"; 448 regulator-suspend-mem-disabled; 449 }; 450 451 vcc33_lcd: SWITCH_REG1 { 452 regulator-always-on; 453 regulator-boot-on; 454 regulator-name = "vcc33_lcd"; 455 regulator-suspend-mem-disabled; 456 }; 457 }; 458 }; 459}; 460 461&i2c1 { 462 status = "okay"; 463 464 clock-frequency = <400000>; 465 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ 466 i2c-scl-rising-time-ns = <100>; /* 40ns measured */ 467 468 tpm: tpm@20 { 469 compatible = "infineon,slb9645tt"; 470 reg = <0x20>; 471 powered-while-suspended; 472 }; 473}; 474 475&i2c2 { 476 status = "okay"; 477 478 /* 100kHz since 4.7k resistors don't rise fast enough */ 479 clock-frequency = <100000>; 480 i2c-scl-falling-time-ns = <50>; /* 10ns measured */ 481 i2c-scl-rising-time-ns = <800>; /* 600ns measured */ 482 483 max98090: max98090@10 { 484 compatible = "maxim,max98090"; 485 reg = <0x10>; 486 interrupt-parent = <&gpio6>; 487 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&int_codec>; 490 }; 491}; 492 493&i2c3 { 494 status = "okay"; 495 496 clock-frequency = <400000>; 497 i2c-scl-falling-time-ns = <50>; 498 i2c-scl-rising-time-ns = <300>; 499}; 500 501&i2c4 { 502 status = "okay"; 503 504 clock-frequency = <400000>; 505 i2c-scl-falling-time-ns = <50>; /* 11ns measured */ 506 i2c-scl-rising-time-ns = <300>; /* 225ns measured */ 507 508 headsetcodec: ts3a227e@3b { 509 compatible = "ti,ts3a227e"; 510 reg = <0x3b>; 511 interrupt-parent = <&gpio0>; 512 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&ts3a227e_int_l>; 515 ti,micbias = <7>; /* MICBIAS = 2.8V */ 516 }; 517}; 518 519&i2c5 { 520 status = "okay"; 521 522 clock-frequency = <100000>; 523 i2c-scl-falling-time-ns = <300>; 524 i2c-scl-rising-time-ns = <1000>; 525}; 526 527&i2s { 528 status = "okay"; 529 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; 530 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; 531}; 532 533&wdt { 534 status = "okay"; 535}; 536 537&pwm0 { 538 status = "okay"; 539}; 540 541&pwm1 { 542 status = "okay"; 543}; 544 545&uart0 { 546 status = "okay"; 547 548 /* Pins don't include flow control by default; add that in */ 549 pinctrl-names = "default"; 550 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 551 /* We need to go faster than 24MHz, so adjust clock parents / rates */ 552 assigned-clocks = <&cru SCLK_UART0>; 553 assigned-clock-rates = <48000000>; 554}; 555 556&uart1 { 557 status = "okay"; 558}; 559 560&uart2 { 561 status = "okay"; 562 u-boot,dm-pre-reloc; 563 reg-shift = <2>; 564}; 565 566&vopb { 567 status = "okay"; 568}; 569 570&vopb_mmu { 571 status = "okay"; 572}; 573 574&vopl { 575 status = "okay"; 576}; 577 578&vopl_mmu { 579 status = "okay"; 580}; 581 582&edp { 583 status = "okay"; 584 rockchip,panel = <&panel>; 585}; 586 587&hdmi { 588 status = "okay"; 589}; 590 591&hdmi_audio { 592 status = "okay"; 593}; 594 595&gpu { 596 status = "okay"; 597}; 598 599&tsadc { 600 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 601 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 602 status = "okay"; 603}; 604 605&pinctrl { 606 u-boot,dm-pre-reloc; 607 pinctrl-names = "default", "sleep"; 608 pinctrl-0 = < 609 /* Common for sleep and wake, but no owners */ 610 &ddr0_retention 611 &ddrio_pwroff 612 &global_pwroff 613 614 /* Wake only */ 615 &bt_dev_wake_awake 616 >; 617 pinctrl-1 = < 618 /* Common for sleep and wake, but no owners */ 619 &ddr0_retention 620 &ddrio_pwroff 621 &global_pwroff 622 623 /* Sleep only */ 624 &bt_dev_wake_sleep 625 >; 626 627 /* Add this for sdmmc pins to SD card */ 628 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 629 drive-strength = <8>; 630 }; 631 632 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 633 bias-pull-up; 634 drive-strength = <8>; 635 }; 636 637 pcfg_output_high: pcfg-output-high { 638 output-high; 639 }; 640 641 pcfg_output_low: pcfg-output-low { 642 output-low; 643 }; 644 645 backlight { 646 bl_en: bl-en { 647 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; 648 }; 649 }; 650 651 buttons { 652 pwr_key_h: pwr-key-h { 653 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; 654 }; 655 }; 656 657 codec { 658 hp_det: hp-det { 659 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; 660 }; 661 int_codec: int-codec { 662 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>; 663 }; 664 mic_det: mic-det { 665 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; 666 }; 667 }; 668 669 emmc { 670 emmc_reset: emmc-reset { 671 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; 672 }; 673 674 /* 675 * We run eMMC at max speed; bump up drive strength. 676 * We also have external pulls, so disable the internal ones. 677 */ 678 emmc_clk: emmc-clk { 679 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 680 }; 681 682 emmc_cmd: emmc-cmd { 683 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 684 }; 685 686 emmc_bus8: emmc-bus8 { 687 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 688 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 689 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 690 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 691 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 692 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 693 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 694 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 695 }; 696 }; 697 698 headset { 699 ts3a227e_int_l: ts3a227e-int-l { 700 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 701 }; 702 }; 703 704 pmic { 705 pmic_int_l: pmic-int-l { 706 /* 707 * Causes jerry to hang when probing bus 0 708 * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; 709 */ 710 }; 711 }; 712 713 reboot { 714 ap_warm_reset_h: ap-warm-reset-h { 715 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; 716 }; 717 }; 718 719 sdio0 { 720 wifi_enable_h: wifienable-h { 721 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; 722 }; 723 724 /* NOTE: mislabelled on schematic; should be bt_enable_h */ 725 bt_enable_l: bt-enable-l { 726 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; 727 }; 728 729 /* 730 * We run sdio0 at max speed; bump up drive strength. 731 * We also have external pulls, so disable the internal ones. 732 */ 733 sdio0_bus4: sdio0-bus4 { 734 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 735 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 736 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 737 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 738 }; 739 740 sdio0_cmd: sdio0-cmd { 741 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 742 }; 743 744 sdio0_clk: sdio0-clk { 745 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 746 }; 747 748 /* 749 * These pins are only present on very new veyron boards; on 750 * older boards bt_dev_wake is simply always high. Note that 751 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt 752 * to map this pin everywhere 753 */ 754 bt_dev_wake_sleep: bt-dev-wake-sleep { 755 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>; 756 }; 757 758 bt_dev_wake_awake: bt-dev-wake-awake { 759 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>; 760 }; 761 }; 762 763 sdmmc { 764 /* 765 * We run sdmmc at max speed; bump up drive strength. 766 * We also have external pulls, so disable the internal ones. 767 */ 768 sdmmc_bus4: sdmmc-bus4 { 769 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 770 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 771 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 772 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 773 }; 774 775 sdmmc_clk: sdmmc-clk { 776 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 777 }; 778 779 sdmmc_cmd: sdmmc-cmd { 780 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 781 }; 782 783 /* 784 * Builtin CD line is hooked to ground to prevent JTAG at boot 785 * (and also to get the voltage rail correct). Make we 786 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't 787 * think there's a card inserted 788 */ 789 sdmmc_cd_disabled: sdmmc-cd-disabled { 790 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; 791 }; 792 793 /* This is where we actually hook up CD */ 794 sdmmc_cd_gpio: sdmmc-cd-gpio { 795 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; 796 }; 797 }; 798 799 tpm { 800 tpm_int_h: tpm-int-h { 801 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; 802 }; 803 }; 804 805 write-protect { 806 fw_wp_ap: fw-wp-ap { 807 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; 808 }; 809 }; 810}; 811 812&usbphy { 813 status = "okay"; 814}; 815 816&usb_host0_ehci { 817 status = "okay"; 818 needs-reset-on-resume; 819}; 820 821&usb_host1 { 822 status = "okay"; 823}; 824 825&usb_otg { 826 dr_mode = "host"; 827 status = "okay"; 828 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; 829 assigned-clock-parents = <&cru SCLK_OTGPHY0>; 830}; 831 832&sdmmc { 833 u-boot,dm-pre-reloc; 834}; 835 836&gpio3 { 837 u-boot,dm-pre-reloc; 838}; 839 840&gpio8 { 841 u-boot,dm-pre-reloc; 842}; 843