1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. 3 4#include <dt-bindings/clock/rk1808-cru.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8 9/ { 10 compatible = "rockchip,rk1808"; 11 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 i2c0 = &i2c0; 18 i2c1 = &i2c1; 19 i2c2 = &i2c2; 20 i2c3 = &i2c3; 21 i2c4 = &i2c4; 22 i2c5 = &i2c5; 23 serial2 = &uart2; 24 spi0 = &spi0; 25 spi1 = &spi1; 26 spi2 = &spi2; 27 }; 28 29 cpus { 30 #address-cells = <2>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a35", "arm,armv8"; 36 reg = <0x0 0x0>; 37 clocks = <&cru ARMCLK>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35", "arm,armv8"; 43 reg = <0x0 0x1>; 44 clocks = <&cru ARMCLK>; 45 }; 46 }; 47 48 arm-pmu { 49 compatible = "arm,cortex-a53-pmu"; 50 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 52 interrupt-affinity = <&cpu0>, <&cpu1>; 53 }; 54 55 gmac_clkin: external-gmac-clock { 56 compatible = "fixed-clock"; 57 clock-frequency = <125000000>; 58 clock-output-names = "gmac_clkin"; 59 #clock-cells = <0>; 60 }; 61 62 timer { 63 compatible = "arm,armv8-timer"; 64 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 65 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 66 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 67 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 68 arm,no-tick-in-suspend; 69 }; 70 71 xin24m: xin24m { 72 compatible = "fixed-clock"; 73 clock-frequency = <24000000>; 74 clock-output-names = "xin24m"; 75 #clock-cells = <0>; 76 }; 77 78 xin32k: xin32k { 79 compatible = "fixed-clock"; 80 clock-frequency = <32768>; 81 clock-output-names = "xin32k"; 82 #clock-cells = <0>; 83 }; 84 85 grf: syscon@fe000000 { 86 compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; 87 reg = <0x0 0xfe000000 0x0 0x1000>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 }; 91 92 pmugrf: syscon@fe410000 { 93 compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; 94 reg = <0x0 0xfe410000 0x0 0x1000>; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 }; 98 99 gic: interrupt-controller@ff100000 { 100 compatible = "arm,gic-v3"; 101 #interrupt-cells = <3>; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges; 105 interrupt-controller; 106 107 reg = <0x0 0xff100000 0 0x10000>, /* GICD */ 108 <0x0 0xff140000 0 0xc0000>, /* GICR */ 109 <0x0 0xff300000 0 0x10000>, /* GICC */ 110 <0x0 0xff310000 0 0x10000>, /* GICH */ 111 <0x0 0xff320000 0 0x10000>; /* GICV */ 112 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 113 its: interrupt-controller@ff120000 { 114 compatible = "arm,gic-v3-its"; 115 msi-controller; 116 reg = <0x0 0xff120000 0x0 0x20000>; 117 }; 118 }; 119 120 cru: clock-controller@ff350000 { 121 compatible = "rockchip,rk1808-cru"; 122 reg = <0x0 0xff350000 0x0 0x5000>; 123 rockchip,grf = <&grf>; 124 #clock-cells = <1>; 125 #reset-cells = <1>; 126 127 assigned-clocks = 128 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 129 <&cru PLL_PPLL>, <&cru ARMCLK>, 130 <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, 131 <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, 132 <&cru LSCLK_BUS_PRE>; 133 assigned-clock-rates = 134 <1200000000>, <1000000000>, 135 <416000000>, <816000000>, 136 <200000000>, <100000000>, 137 <300000000>, <200000000>, 138 <100000000>; 139 }; 140 141 tsadc: tsadc@ff3a0000 { 142 compatible = "rockchip,rk1808-tsadc"; 143 reg = <0x0 0xff3a0000 0x0 0x100>; 144 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 145 rockchip,grf = <&grf>; 146 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 147 clock-names = "tsadc", "apb_pclk"; 148 assigned-clocks = <&cru SCLK_TSADC>; 149 assigned-clock-rates = <50000>; 150 resets = <&cru SRST_TSADC>; 151 reset-names = "tsadc-apb"; 152 #thermal-sensor-cells = <1>; 153 rockchip,hw-tshut-temp = <120000>; 154 status = "disabled"; 155 }; 156 157 pwm0: pwm@ff3d0000 { 158 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 159 reg = <0x0 0xff3d0000 0x0 0x10>; 160 #pwm-cells = <3>; 161 pinctrl-names = "active"; 162 pinctrl-0 = <&pwm0_pin>; 163 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 164 clock-names = "pwm", "pclk"; 165 status = "disabled"; 166 }; 167 168 pwm1: pwm@ff3d0010 { 169 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 170 reg = <0x0 0xff3d0010 0x0 0x10>; 171 #pwm-cells = <3>; 172 pinctrl-names = "active"; 173 pinctrl-0 = <&pwm1_pin>; 174 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 175 clock-names = "pwm", "pclk"; 176 status = "disabled"; 177 }; 178 179 pwm2: pwm@ff3d0020 { 180 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 181 reg = <0x0 0xff3d0020 0x0 0x10>; 182 #pwm-cells = <3>; 183 pinctrl-names = "active"; 184 pinctrl-0 = <&pwm2_pin>; 185 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 186 clock-names = "pwm", "pclk"; 187 status = "disabled"; 188 }; 189 190 pwm3: pwm@ff3d0030 { 191 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 192 reg = <0x0 0xff3d0030 0x0 0x10>; 193 #pwm-cells = <3>; 194 pinctrl-names = "active"; 195 pinctrl-0 = <&pwm3_pin>; 196 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 197 clock-names = "pwm", "pclk"; 198 status = "disabled"; 199 }; 200 201 pwm4: pwm@ff3d8000 { 202 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 203 reg = <0x0 0xff3d8000 0x0 0x10>; 204 #pwm-cells = <3>; 205 pinctrl-names = "active"; 206 pinctrl-0 = <&pwm4_pin>; 207 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 208 clock-names = "pwm", "pclk"; 209 status = "disabled"; 210 }; 211 212 pwm5: pwm@ff3d8010 { 213 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 214 reg = <0x0 0xff3d8010 0x0 0x10>; 215 #pwm-cells = <3>; 216 pinctrl-names = "active"; 217 pinctrl-0 = <&pwm5_pin>; 218 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 219 clock-names = "pwm", "pclk"; 220 status = "disabled"; 221 }; 222 223 pwm6: pwm@ff3d8020 { 224 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 225 reg = <0x0 0xff3d8020 0x0 0x10>; 226 #pwm-cells = <3>; 227 pinctrl-names = "active"; 228 pinctrl-0 = <&pwm6_pin>; 229 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 230 clock-names = "pwm", "pclk"; 231 status = "disabled"; 232 }; 233 234 pwm7: pwm@ff3d8030 { 235 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 236 reg = <0x0 0xff3d8030 0x0 0x10>; 237 #pwm-cells = <3>; 238 pinctrl-names = "active"; 239 pinctrl-0 = <&pwm7_pin>; 240 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 241 clock-names = "pwm", "pclk"; 242 status = "disabled"; 243 }; 244 245 i2c0: i2c@ff410000 { 246 compatible = "rockchip,rk3399-i2c"; 247 reg = <0x0 0xff410000 0x0 0x1000>; 248 clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; 249 clock-names = "i2c", "pclk"; 250 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&i2c0_xfer>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 status = "disabled"; 256 }; 257 258 amba { 259 compatible = "simple-bus"; 260 #address-cells = <2>; 261 #size-cells = <2>; 262 ranges; 263 264 dmac: dmac@ff4e0000 { 265 compatible = "arm,pl330", "arm,primecell"; 266 reg = <0x0 0xff4e0000 0x0 0x4000>; 267 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 268 //clocks = <&cru ACLK_DMAC>; 269 //clock-names = "apb_pclk"; 270 #dma-cells = <1>; 271 peripherals-req-type-burst; 272 }; 273 }; 274 275 i2c1: i2c@ff500000 { 276 compatible = "rockchip,rk3399-i2c"; 277 reg = <0x0 0xff500000 0x0 0x1000>; 278 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 279 clock-names = "i2c", "pclk"; 280 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2c1_xfer>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 status = "disabled"; 286 }; 287 288 i2c2: i2c@ff504000 { 289 compatible = "rockchip,rk3399-i2c"; 290 reg = <0x0 0xff504000 0x0 0x1000>; 291 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 292 clock-names = "i2c", "pclk"; 293 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c2m0_xfer>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 status = "disabled"; 299 }; 300 301 i2c3: i2c@ff508000 { 302 compatible = "rockchip,rk3399-i2c"; 303 reg = <0x0 0xff508000 0x0 0x1000>; 304 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 305 clock-names = "i2c", "pclk"; 306 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c3_xfer>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 status = "disabled"; 312 }; 313 314 i2c4: i2c@ff50c000 { 315 compatible = "rockchip,rk3399-i2c"; 316 reg = <0x0 0xff50c000 0x0 0x1000>; 317 clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; 318 clock-names = "i2c", "pclk"; 319 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&i2c4_xfer>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 status = "disabled"; 325 }; 326 327 i2c5: i2c@ff510000 { 328 compatible = "rockchip,rk3399-i2c"; 329 reg = <0x0 0xff100000 0x0 0x1000>; 330 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 331 clock-names = "i2c", "pclk"; 332 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&i2c5_xfer>; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 status = "disabled"; 338 }; 339 340 spi0: spi@ff520000 { 341 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 342 reg = <0x0 0xff520000 0x0 0x1000>; 343 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 347 clock-names = "spiclk", "apb_pclk"; 348 dmas = <&dmac 10>, <&dmac 11>; 349 dma-names = "tx", "rx"; 350 pinctrl-names = "default", "high_speed"; 351 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 352 pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; 353 status = "disabled"; 354 }; 355 356 spi1: spi@ff530000 { 357 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 358 reg = <0x0 0xff530000 0x0 0x1000>; 359 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 363 clock-names = "spiclk", "apb_pclk"; 364 dmas = <&dmac 12>, <&dmac 13>; 365 dma-names = "tx", "rx"; 366 pinctrl-names = "default", "high_speed"; 367 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 368 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; 369 status = "disabled"; 370 }; 371 372 spi2: spi@ff580000 { 373 compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; 374 reg = <0x0 0xff580000 0x0 0x1000>; 375 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 379 clock-names = "spiclk", "apb_pclk"; 380 dmas = <&dmac 14>, <&dmac 15>; 381 dma-names = "tx", "rx"; 382 pinctrl-names = "default", "high_speed"; 383 pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; 384 pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; 385 status = "disabled"; 386 }; 387 388 uart2: serial@ff550000 { 389 compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; 390 reg = <0x0 0xff550000 0x0 0x100>; 391 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 392 reg-shift = <2>; 393 reg-io-width = <4>; 394 status = "disabled"; 395 }; 396 397 pwm8: pwm@ff5d0000 { 398 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 399 reg = <0x0 0xff5d0000 0x0 0x10>; 400 #pwm-cells = <3>; 401 pinctrl-names = "active"; 402 pinctrl-0 = <&pwm8_pin>; 403 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 404 clock-names = "pwm", "pclk"; 405 status = "disabled"; 406 }; 407 408 pwm9: pwm@fff5d0010 { 409 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 410 reg = <0x0 0xff5d0010 0x0 0x10>; 411 #pwm-cells = <3>; 412 pinctrl-names = "active"; 413 pinctrl-0 = <&pwm9_pin>; 414 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 415 clock-names = "pwm", "pclk"; 416 status = "disabled"; 417 }; 418 419 pwm10: pwm@ff5d0020 { 420 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 421 reg = <0x0 0xff5d0020 0x0 0x10>; 422 #pwm-cells = <3>; 423 pinctrl-names = "active"; 424 pinctrl-0 = <&pwm10_pin>; 425 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 426 clock-names = "pwm", "pclk"; 427 status = "disabled"; 428 }; 429 430 pwm11: pwm@ff5d0030 { 431 compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; 432 reg = <0x0 0xff5d0030 0x0 0x10>; 433 #pwm-cells = <3>; 434 pinctrl-names = "active"; 435 pinctrl-0 = <&pwm11_pin>; 436 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; 437 clock-names = "pwm", "pclk"; 438 status = "disabled"; 439 }; 440 441 sdmmc: dwmmc@ffcf0000 { 442 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 443 reg = <0x0 0xffcf0000 0x0 0x4000>; 444 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 445 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 446 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 447 max-frequency = <150000000>; 448 fifo-depth = <0x100>; 449 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd>; 452 status = "disabled"; 453 }; 454 455 emmc: dwmmc@ffd00000 { 456 compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; 457 reg = <0x0 0xffd00000 0x0 0x4000>; 458 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 459 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 460 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 461 max-frequency = <150000000>; 462 fifo-depth = <0x100>; 463 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 464 status = "disabled"; 465 }; 466 467 gmac: ethernet@ffdd0000 { 468 compatible = "rockchip,rk1808-gmac"; 469 reg = <0x0 0xffdd0000 0x0 0x10000>; 470 rockchip,grf = <&grf>; 471 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 472 interrupt-names = "macirq"; 473 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 474 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, 475 <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, 476 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; 477 clock-names = "stmmaceth", "mac_clk_rx", 478 "mac_clk_tx", "clk_mac_ref", 479 "clk_mac_refout", "aclk_mac", 480 "pclk_mac", "clk_mac_speed"; 481 phy-mode = "rgmii"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&rgmii_pins>; 484 resets = <&cru SRST_GAMC_A>; 485 reset-names = "stmmaceth"; 486 /* power-domains = <&power RK1808_PD_GMAC>; */ 487 status = "disabled"; 488 }; 489 490 pinctrl: pinctrl { 491 compatible = "rockchip,rk1808-pinctrl"; 492 rockchip,grf = <&grf>; 493 rockchip,pmu = <&pmugrf>; 494 #address-cells = <2>; 495 #size-cells = <2>; 496 ranges; 497 498 gpio0: gpio0@ff4c0000 { 499 compatible = "rockchip,gpio-bank"; 500 reg = <0x0 0xff4c0000 0x0 0x100>; 501 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cru SCLK_PMU_GPIO0>, <&cru PCLK_GPIO0_PMU>; 503 gpio-controller; 504 #gpio-cells = <2>; 505 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 }; 509 510 gpio1: gpio1@ff690000 { 511 compatible = "rockchip,gpio-bank"; 512 reg = <0x0 0xff690000 0x0 0x100>; 513 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&cru SCLK_GPIO1>, <&cru PCLK_GPIO1>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 }; 521 522 gpio2: gpio2@ff6a0000 { 523 compatible = "rockchip,gpio-bank"; 524 reg = <0x0 0xff6a0000 0x0 0x100>; 525 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&cru SCLK_GPIO2>, <&cru PCLK_GPIO2>; 527 gpio-controller; 528 #gpio-cells = <2>; 529 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 }; 533 534 gpio3: gpio3@ff6b0000 { 535 compatible = "rockchip,gpio-bank"; 536 reg = <0x0 0xff6b0000 0x0 0x100>; 537 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&cru SCLK_GPIO3>, <&cru PCLK_GPIO3>; 539 gpio-controller; 540 #gpio-cells = <2>; 541 542 interrupt-controller; 543 #interrupt-cells = <2>; 544 }; 545 546 gpio4: gpio4@ff6c0000 { 547 compatible = "rockchip,gpio-bank"; 548 reg = <0x0 0xff6c0000 0x0 0x100>; 549 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&cru SCLK_GPIO4>, <&cru PCLK_GPIO4>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 }; 557 558 pcfg_pull_up: pcfg-pull-up { 559 bias-pull-up; 560 }; 561 562 pcfg_pull_down: pcfg-pull-down { 563 bias-pull-down; 564 }; 565 566 pcfg_pull_none: pcfg-pull-none { 567 bias-disable; 568 }; 569 570 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 571 bias-disable; 572 drive-strength = <2>; 573 }; 574 575 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 576 bias-pull-up; 577 drive-strength = <2>; 578 }; 579 580 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 581 bias-pull-up; 582 drive-strength = <4>; 583 }; 584 585 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 586 bias-disable; 587 drive-strength = <4>; 588 }; 589 590 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 591 bias-pull-down; 592 drive-strength = <4>; 593 }; 594 595 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 596 bias-disable; 597 drive-strength = <8>; 598 }; 599 600 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 601 bias-pull-up; 602 drive-strength = <8>; 603 }; 604 605 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 606 bias-disable; 607 drive-strength = <12>; 608 }; 609 610 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 611 bias-pull-up; 612 drive-strength = <12>; 613 }; 614 615 pcfg_pull_none_smt: pcfg-pull-none-smt { 616 bias-disable; 617 input-schmitt-enable; 618 }; 619 620 pcfg_output_high: pcfg-output-high { 621 output-high; 622 }; 623 624 pcfg_output_low: pcfg-output-low { 625 output-low; 626 }; 627 628 pcfg_input_high: pcfg-input-high { 629 bias-pull-up; 630 input-enable; 631 }; 632 633 pcfg_input: pcfg-input { 634 input-enable; 635 }; 636 637 emmc { 638 emmc_clk: emmc-clk { 639 rockchip,pins = 640 /* emmc_clkout */ 641 <1 9 1 &pcfg_pull_none>; 642 }; 643 644 emmc_rstnout: emmc-rstnout { 645 rockchip,pins = 646 /* emmc_rstn */ 647 <1 11 1 &pcfg_pull_none>; 648 }; 649 650 emmc_bus8: emmc-bus8 { 651 rockchip,pins = 652 /* emmc_d0 */ 653 <1 RK_PA0 1 &pcfg_pull_none>, 654 /* emmc_d1 */ 655 <1 RK_PA1 1 &pcfg_pull_none>, 656 /* emmc_d2 */ 657 <1 RK_PA2 1 &pcfg_pull_none>, 658 /* emmc_d3 */ 659 <1 RK_PA3 1 &pcfg_pull_none>, 660 /* emmc_d4 */ 661 <1 RK_PA4 1 &pcfg_pull_none>, 662 /* emmc_d5 */ 663 <1 RK_PA5 1 &pcfg_pull_none>, 664 /* emmc_d6 */ 665 <1 RK_PA6 1 &pcfg_pull_none>, 666 /* emmc_d7 */ 667 <1 RK_PA7 1 &pcfg_pull_none>; 668 }; 669 670 emmc_pwren: emmc-pwren { 671 rockchip,pins = 672 <1 RK_PB0 1 &pcfg_pull_none>; 673 }; 674 675 emmc_cmd: emmc-cmd { 676 rockchip,pins = 677 <1 RK_PB2 1 &pcfg_pull_none>; 678 }; 679 }; 680 681 gmac { 682 rgmii_pins: rgmii-pins { 683 rockchip,pins = 684 /* rgmii_txen */ 685 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 686 /* rgmii_txd1 */ 687 <2 RK_PA2 2 &pcfg_pull_none_12ma>, 688 /* rgmii_txd0 */ 689 <2 RK_PA3 2 &pcfg_pull_none_12ma>, 690 /* rgmii_rxd0 */ 691 <2 RK_PA4 2 &pcfg_pull_none>, 692 /* rgmii_rxd1 */ 693 <2 RK_PA5 2 &pcfg_pull_none>, 694 /* rgmii_rxdv */ 695 <2 RK_PA7 2 &pcfg_pull_none>, 696 /* rgmii_mdio */ 697 <2 RK_PB0 2 &pcfg_pull_none>, 698 /* rgmii_mdc */ 699 <2 RK_PB2 2 &pcfg_pull_none>, 700 /* rgmii_txd3 */ 701 <2 RK_PB3 2 &pcfg_pull_none_12ma>, 702 /* rgmii_txd2 */ 703 <2 RK_PB4 2 &pcfg_pull_none_12ma>, 704 /* rgmii_rxd2 */ 705 <2 RK_PB5 2 &pcfg_pull_none>, 706 /* rgmii_rxd3 */ 707 <2 RK_PB6 2 &pcfg_pull_none>, 708 /* rgmii_clk */ 709 <2 RK_PB7 2 &pcfg_pull_none>, 710 /* rgmii_txclk */ 711 <2 RK_PC1 2 &pcfg_pull_none_12ma>, 712 /* rgmii_rxclk */ 713 <2 RK_PC2 2 &pcfg_pull_none>; 714 }; 715 716 rmii_pins: rmii-pins { 717 rockchip,pins = 718 /* rmii_txen */ 719 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 720 /* rmii_txd1 */ 721 <2 RK_PA2 2 &pcfg_pull_none_12ma>, 722 /* rmii_txd0 */ 723 <2 RK_PA3 2 &pcfg_pull_none_12ma>, 724 /* rmii_rxd0 */ 725 <2 RK_PA4 2 &pcfg_pull_none>, 726 /* rmii_rxd1 */ 727 <2 RK_PA5 2 &pcfg_pull_none>, 728 /* rmii_rxer */ 729 <2 RK_PA6 2 &pcfg_pull_none>, 730 /* rmii_rxdv */ 731 <2 RK_PA7 2 &pcfg_pull_none>, 732 /* rmii_mdio */ 733 <2 RK_PB0 2 &pcfg_pull_none>, 734 /* rmii_mdc */ 735 <2 RK_PB2 2 &pcfg_pull_none>, 736 /* rmii_clk */ 737 <2 RK_PB7 2 &pcfg_pull_none>; 738 }; 739 }; 740 741 i2c0 { 742 i2c0_xfer: i2c0-xfer { 743 rockchip,pins = 744 /* i2c0_sda */ 745 <0 RK_PB1 1 &pcfg_pull_none_smt>, 746 /* i2c0_scl */ 747 <0 RK_PB0 1 &pcfg_pull_none_smt>; 748 }; 749 }; 750 751 i2c1 { 752 i2c1_xfer: i2c1-xfer { 753 rockchip,pins = 754 /* i2c1_sda */ 755 <0 RK_PC1 1 &pcfg_pull_none_smt>, 756 /* i2c1_scl */ 757 <0 RK_PC0 1 &pcfg_pull_none_smt>; 758 }; 759 }; 760 761 i2c2m0 { 762 i2c2m0_xfer: i2c2m0-xfer { 763 rockchip,pins = 764 /* i2c2m0_sda */ 765 <3 RK_PB4 2 &pcfg_pull_none_smt>, 766 /* i2c2m0_scl */ 767 <3 RK_PB3 2 &pcfg_pull_none_smt>; 768 }; 769 }; 770 771 i2c3 { 772 i2c3_xfer: i2c3-xfer { 773 rockchip,pins = 774 /* i2c3_sda */ 775 <2 RK_PD1 1 &pcfg_pull_none_smt>, 776 /* i2c3_scl */ 777 <2 RK_PD0 1 &pcfg_pull_none_smt>; 778 }; 779 }; 780 781 i2c4 { 782 i2c4_xfer: i2c4-xfer { 783 rockchip,pins = 784 /* i2c4_sda */ 785 <3 RK_PC3 3 &pcfg_pull_none_smt>, 786 /* i2c4_scl */ 787 <3 RK_PC2 3 &pcfg_pull_none_smt>; 788 }; 789 }; 790 791 i2c5 { 792 i2c5_xfer: i2c5-xfer { 793 rockchip,pins = 794 /* i2c5_sda */ 795 <4 RK_PC2 1 &pcfg_pull_none_smt>, 796 /* i2c5_scl */ 797 <4 RK_PC1 1 &pcfg_pull_none_smt>; 798 }; 799 }; 800 801 i2s1 { 802 i2s1_2ch_lrck: i2s1-2ch-lrck { 803 rockchip,pins = 804 <3 RK_PA0 1 &pcfg_pull_none>; 805 }; 806 i2s1_2ch_sclk: i2s1-2ch-sclk { 807 rockchip,pins = 808 <3 RK_PA1 1 &pcfg_pull_none>; 809 }; 810 i2s1_2ch_mclk: i2s1-2ch-mclk { 811 rockchip,pins = 812 <3 RK_PA2 1 &pcfg_pull_none>; 813 }; 814 i2s1_2ch_sdo: i2s1-2ch-sdo { 815 rockchip,pins = 816 <3 RK_PA3 1 &pcfg_pull_none>; 817 }; 818 i2s1_2ch_sdi: i2s1-2ch-sdi { 819 rockchip,pins = 820 <3 RK_PA4 1 &pcfg_pull_none>; 821 }; 822 }; 823 824 i2s0 { 825 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 826 rockchip,pins = 827 <3 RK_PA5 1 &pcfg_pull_none>; 828 }; 829 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 830 rockchip,pins = 831 <3 RK_PA6 1 &pcfg_pull_none>; 832 }; 833 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 834 rockchip,pins = 835 <3 RK_PA7 1 &pcfg_pull_none>; 836 }; 837 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 838 rockchip,pins = 839 <3 RK_PB0 1 &pcfg_pull_none>; 840 }; 841 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 842 rockchip,pins = 843 <3 RK_PB1 1 &pcfg_pull_none>; 844 }; 845 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 846 rockchip,pins = 847 <3 RK_PB2 1 &pcfg_pull_none>; 848 }; 849 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 850 rockchip,pins = 851 <3 RK_PB3 1 &pcfg_pull_none>; 852 }; 853 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 854 rockchip,pins = 855 <3 RK_PB4 1 &pcfg_pull_none>; 856 }; 857 i2s0_8ch_mclk: i2s0-8ch-mclk { 858 rockchip,pins = 859 <3 RK_PB5 1 &pcfg_pull_none>; 860 }; 861 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 862 rockchip,pins = 863 <3 RK_PB6 1 &pcfg_pull_none>; 864 }; 865 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 866 rockchip,pins = 867 <3 RK_PB7 1 &pcfg_pull_none>; 868 }; 869 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 870 rockchip,pins = 871 <3 RK_PC0 1 &pcfg_pull_none>; 872 }; 873 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 874 rockchip,pins = 875 <3 RK_PC1 1 &pcfg_pull_none>; 876 }; 877 }; 878 879 pciusb { 880 pciusb_pins: pciusb-pins { 881 rockchip,pins = 882 /* pciusb_debug0 */ 883 <4 RK_PB4 3 &pcfg_pull_none>, 884 /* pciusb_debug1 */ 885 <4 RK_PB5 3 &pcfg_pull_none>, 886 /* pciusb_debug2 */ 887 <4 RK_PB6 3 &pcfg_pull_none>, 888 /* pciusb_debug3 */ 889 <4 RK_PB7 3 &pcfg_pull_none>, 890 /* pciusb_debug4 */ 891 <4 RK_PC0 3 &pcfg_pull_none>, 892 /* pciusb_debug5 */ 893 <4 RK_PC1 3 &pcfg_pull_none>, 894 /* pciusb_debug6 */ 895 <4 RK_PC2 3 &pcfg_pull_none>, 896 /* pciusb_debug7 */ 897 <4 RK_PC3 3 &pcfg_pull_none>; 898 }; 899 }; 900 901 pdm { 902 pdm_clk: pdm-clk { 903 rockchip,pins = 904 /* pdm_clk0 */ 905 <3 RK_PB0 2 &pcfg_pull_none>; 906 }; 907 908 pdm_sdi3: pdm-sdi3 { 909 rockchip,pins = 910 <3 RK_PA5 2 &pcfg_pull_none>; 911 }; 912 913 pdm_sdi2: pdm-sdi2 { 914 rockchip,pins = 915 <3 RK_PA6 2 &pcfg_pull_none>; 916 }; 917 918 pdm_sdi1: pdm-sdi1 { 919 rockchip,pins = 920 <3 RK_PA7 2 &pcfg_pull_none>; 921 }; 922 923 pdm_clk1: pdm-clk1 { 924 rockchip,pins = 925 <3 RK_PB1 2 &pcfg_pull_none>; 926 }; 927 928 pdm_sdi0: pdm-sdi0 { 929 rockchip,pins = 930 <3 RK_PC1 2 &pcfg_pull_none>; 931 }; 932 }; 933 934 pwm0 { 935 pwm0_pin: pwm0-pin { 936 rockchip,pins = 937 <0 RK_PB7 1 &pcfg_pull_none>; 938 }; 939 }; 940 941 pwm1 { 942 pwm1_pin: pwm1-pin { 943 rockchip,pins = 944 <0 RK_PC3 1 &pcfg_pull_none>; 945 }; 946 }; 947 948 pwm2 { 949 pwm2_pin: pwm2-pin { 950 rockchip,pins = 951 <0 RK_PC5 1 &pcfg_pull_none>; 952 }; 953 }; 954 955 pwm3 { 956 pwm3_pin: pwm3-pin { 957 rockchip,pins = 958 <0 RK_PC4 1 &pcfg_pull_none>; 959 }; 960 }; 961 962 pwm4 { 963 pwm4_pin: pwm4-pin { 964 rockchip,pins = 965 <1 RK_PB6 2 &pcfg_pull_none>; 966 }; 967 }; 968 969 pwm5 { 970 pwm5_pin: pwm5-pin { 971 rockchip,pins = 972 <1 RK_PB7 2 &pcfg_pull_none>; 973 }; 974 }; 975 pwm6 { 976 pwm6_pin: pwm6-pin { 977 rockchip,pins = 978 <3 RK_PA1 2 &pcfg_pull_none>; 979 }; 980 }; 981 982 pwm7 { 983 pwm7_pin: pwm7-pin { 984 rockchip,pins = 985 <3 RK_PA2 2 &pcfg_pull_none>; 986 }; 987 }; 988 989 pwm8 { 990 pwm8_pin: pwm8-pin { 991 rockchip,pins = 992 <3 RK_PD0 2 &pcfg_pull_none>; 993 }; 994 }; 995 996 pwm9 { 997 pwm9_pin: pwm9-pin { 998 rockchip,pins = 999 <3 RK_PD1 2 &pcfg_pull_none>; 1000 }; 1001 }; 1002 1003 pwm10 { 1004 pwm10_pin: pwm10-pin { 1005 rockchip,pins = 1006 <3 RK_PD2 2 &pcfg_pull_none>; 1007 }; 1008 }; 1009 1010 pwm11 { 1011 pwm11_pin: pwm11-pin { 1012 rockchip,pins = 1013 <3 RK_PD3 2 &pcfg_pull_none>; 1014 }; 1015 }; 1016 1017 sdmmc0 { 1018 sdmmc0_bus4: sdmmc0-bus4 { 1019 rockchip,pins = 1020 /* sdmmc0_d0 */ 1021 <4 RK_PA2 1 &pcfg_pull_none>, 1022 /* sdmmc0_d1 */ 1023 <4 RK_PA3 1 &pcfg_pull_none>, 1024 /* sdmmc0_d2 */ 1025 <4 RK_PA4 1 &pcfg_pull_none>, 1026 /* sdmmc0_d3 */ 1027 <4 RK_PA5 1 &pcfg_pull_none>; 1028 }; 1029 sdmmc0_cmd: sdmmc0-cmd { 1030 rockchip,pins = 1031 <4 RK_PA0 1 &pcfg_pull_none>; 1032 }; 1033 sdmmc0_clk: sdmmc0-clk { 1034 rockchip,pins = 1035 <4 RK_PA1 1 &pcfg_pull_none>; 1036 }; 1037 }; 1038 1039 sdmmc1 { 1040 sdmmc1_bus4: sdmmc1-bus4 { 1041 rockchip,pins = 1042 /* sdmmc1_d0 */ 1043 <4 RK_PB0 1 &pcfg_pull_none>, 1044 /* sdmmc1_d1 */ 1045 <4 RK_PB1 1 &pcfg_pull_none>, 1046 /* sdmmc1_d2 */ 1047 <4 RK_PB2 1 &pcfg_pull_none>, 1048 /* sdmmc1_d3 */ 1049 <4 RK_PB3 1 &pcfg_pull_none>; 1050 }; 1051 1052 sdmmc1_cmd: sdmmc1-cmd { 1053 rockchip,pins = 1054 <4 RK_PA6 1 &pcfg_pull_none>; 1055 }; 1056 1057 sdmmc1_clk: sdmmc1-clk { 1058 rockchip,pins = 1059 <4 RK_PB1 1 &pcfg_pull_none>; 1060 }; 1061 }; 1062 1063 spi0 { 1064 spi0_mosi: spi0-mosi { 1065 rockchip,pins = 1066 <1 RK_PB4 1 &pcfg_pull_up_4ma>; 1067 }; 1068 1069 spi0_miso: spi0-miso { 1070 rockchip,pins = 1071 <1 RK_PB5 1 &pcfg_pull_up_4ma>; 1072 }; 1073 1074 spi0_csn: spi0-csn { 1075 rockchip,pins = 1076 <1 RK_PB6 1 &pcfg_pull_up_4ma>; 1077 }; 1078 1079 spi0_clk: spi0-clk { 1080 rockchip,pins = 1081 <1 RK_PB7 1 &pcfg_pull_up_4ma>; 1082 }; 1083 1084 spi0_mosi_hs: spi0-mosi-hs { 1085 rockchip,pins = 1086 <1 RK_PB4 1 &pcfg_pull_up_8ma>; 1087 }; 1088 1089 spi0_miso_hs: spi0-miso-hs { 1090 rockchip,pins = 1091 <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1092 }; 1093 1094 spi0_csn_hs: spi0-csn-hs { 1095 rockchip,pins = 1096 <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1097 }; 1098 1099 spi0_clk_hs: spi0-clk-hs { 1100 rockchip,pins = 1101 <1 RK_PB7 1 &pcfg_pull_up_8ma>; 1102 }; 1103 }; 1104 1105 spi1 { 1106 spi1_clk: spi1-clk { 1107 rockchip,pins = 1108 <4 RK_PB4 2 &pcfg_pull_up_4ma>; 1109 }; 1110 1111 spi1_mosi: spi1-mosi { 1112 rockchip,pins = 1113 <4 RK_PB5 2 &pcfg_pull_up_4ma>; 1114 }; 1115 1116 spi1_csn0: spi1-csn0 { 1117 rockchip,pins = 1118 <4 RK_PB6 2 &pcfg_pull_up_4ma>; 1119 }; 1120 1121 spi1_miso: spi1-miso { 1122 rockchip,pins = 1123 <4 RK_PB7 2 &pcfg_pull_up_4ma>; 1124 }; 1125 1126 spi1_csn1: spi1-csn1 { 1127 rockchip,pins = 1128 <4 RK_PC0 2 &pcfg_pull_up_4ma>; 1129 }; 1130 1131 spi1_clk_hs: spi1-clk-hs { 1132 rockchip,pins = 1133 <4 RK_PB4 2 &pcfg_pull_up_8ma>; 1134 }; 1135 1136 spi1_mosi_hs: spi1-mosi-hs { 1137 rockchip,pins = 1138 <4 RK_PB5 2 &pcfg_pull_up_8ma>; 1139 }; 1140 1141 spi1_csn0_hs: spi1-csn0-hs { 1142 rockchip,pins = 1143 <4 RK_PB6 2 &pcfg_pull_up_8ma>; 1144 }; 1145 1146 spi1_miso_hs: spi1-miso-hs { 1147 rockchip,pins = 1148 <4 RK_PB7 2 &pcfg_pull_up_8ma>; 1149 }; 1150 1151 spi1_csn1_hs: spi1-csn1-hs { 1152 rockchip,pins = 1153 <4 RK_PC0 2 &pcfg_pull_up_8ma>; 1154 }; 1155 }; 1156 1157 spi1m1 { 1158 spi1m1_clk: spi1m1-clk { 1159 rockchip,pins = 1160 <3 RK_PC7 3 &pcfg_pull_up_4ma>; 1161 }; 1162 1163 spi1m1_mosi: spi1m1-mosi { 1164 rockchip,pins = 1165 <3 RK_PD0 3 &pcfg_pull_up_4ma>; 1166 }; 1167 1168 spi1m1_csn0: spi1m1-csn0 { 1169 rockchip,pins = 1170 <3 RK_PD1 3 &pcfg_pull_up_4ma>; 1171 }; 1172 1173 spi1m1_miso: spi1m1-miso { 1174 rockchip,pins = 1175 <3 RK_PD2 3 &pcfg_pull_up_4ma>; 1176 }; 1177 1178 spi1m1_csn1: spi1m1-csn1 { 1179 rockchip,pins = 1180 <3 RK_PD3 3 &pcfg_pull_up_4ma>; 1181 }; 1182 1183 spi1m1_clk_hs: spi1m1-clk-hs { 1184 rockchip,pins = 1185 <3 RK_PC7 3 &pcfg_pull_none>; 1186 }; 1187 1188 spi1m1_mosi_hs: spi1m1-mosi-hs { 1189 rockchip,pins = 1190 <3 RK_PD0 3 &pcfg_pull_none>; 1191 }; 1192 1193 spi1m1_csn0_hs: spi1m1-csn0-hs { 1194 rockchip,pins = 1195 <3 RK_PD1 3 &pcfg_pull_none>; 1196 }; 1197 1198 spi1m1_miso_hs: spi1m1-miso-hs { 1199 rockchip,pins = 1200 <3 RK_PD2 3 &pcfg_pull_none>; 1201 }; 1202 1203 spi1m1_csn1_hs: spi1m1-csn1-hs { 1204 rockchip,pins = 1205 <3 RK_PD3 3 &pcfg_pull_none>; 1206 }; 1207 }; 1208 1209 spi2m0 { 1210 spi2m0_miso: spi2m0-miso { 1211 rockchip,pins = 1212 <1 RK_PA6 2 &pcfg_pull_up_4ma>; 1213 }; 1214 1215 spi2m0_clk: spi2m0-clk { 1216 rockchip,pins = 1217 <1 RK_PA7 2 &pcfg_pull_up_4ma>; 1218 }; 1219 1220 spi2m0_mosi: spi2m0-mosi { 1221 rockchip,pins = 1222 <1 RK_PB0 2 &pcfg_pull_up_4ma>; 1223 }; 1224 1225 spi2m0_csn: spi2m0-csn { 1226 rockchip,pins = 1227 <1 RK_PB1 2 &pcfg_pull_up_4ma>; 1228 }; 1229 1230 spi2m0_miso_hs: spi2m0-miso-hs { 1231 rockchip,pins = 1232 <1 RK_PA6 2 &pcfg_pull_none>; 1233 }; 1234 1235 spi2m0_clk_hs: spi2m0-clk-hs { 1236 rockchip,pins = 1237 <1 RK_PA7 2 &pcfg_pull_none>; 1238 }; 1239 1240 spi2m0_mosi_hs: spi2m0-mosi-hs { 1241 rockchip,pins = 1242 <1 RK_PB0 2 &pcfg_pull_none>; 1243 }; 1244 1245 spi2m0_csn_hs: spi2m0-csn-hs { 1246 rockchip,pins = 1247 <1 RK_PB1 2 &pcfg_pull_none>; 1248 }; 1249 }; 1250 1251 spi2m1 { 1252 spi2m1_miso: spi2m1-miso { 1253 rockchip,pins = 1254 <2 RK_PA4 3 &pcfg_pull_up_4ma>; 1255 }; 1256 1257 spi2m1_clk: spi2m1-clk { 1258 rockchip,pins = 1259 <2 RK_PA5 3 &pcfg_pull_up_4ma>; 1260 }; 1261 1262 spi2m1_mosi: spi2m1-mosi { 1263 rockchip,pins = 1264 <2 RK_PA6 3 &pcfg_pull_up_4ma>; 1265 }; 1266 1267 spi2m1_csn: spi2m1-csn { 1268 rockchip,pins = 1269 <2 RK_PA7 3 &pcfg_pull_up_4ma>; 1270 }; 1271 1272 spi2m1_miso_hs: spi2m1-miso-hs { 1273 rockchip,pins = 1274 <2 RK_PA4 3 &pcfg_pull_none>; 1275 }; 1276 1277 spi2m1_clk_hs: spi2m1-clk-hs { 1278 rockchip,pins = 1279 <2 RK_PA5 3 &pcfg_pull_none>; 1280 }; 1281 1282 spi2m1_mosi_hs: spi2m1-mosi-hs { 1283 rockchip,pins = 1284 <2 RK_PA6 3 &pcfg_pull_none>; 1285 }; 1286 1287 spi2m1_csn_hs: spi2m1-csn-hs { 1288 rockchip,pins = 1289 <2 RK_PA7 3 &pcfg_pull_none>; 1290 }; 1291 }; 1292 1293 uart2m0 { 1294 uart2m0_xfer: uart2m0-xfer { 1295 rockchip,pins = 1296 /* uart2_rxm0 */ 1297 <4 RK_PA3 2 &pcfg_pull_none>, 1298 /* uart2_txm0 */ 1299 <4 RK_PA2 2 &pcfg_pull_none>; 1300 }; 1301 }; 1302 1303 uart2m1 { 1304 uart2m1_xfer: uart2m1-xfer { 1305 rockchip,pins = 1306 /* uart2_rxm1 */ 1307 <2 RK_PD1 2 &pcfg_pull_none>, 1308 /* uart2_txm1 */ 1309 <2 RK_PD0 2 &pcfg_pull_none>; 1310 }; 1311 }; 1312 1313 uart2m2 { 1314 uart2m2_xfer: uart2m2-xfer { 1315 rockchip,pins = 1316 /* uart2_rxm2 */ 1317 <3 RK_PA4 2 &pcfg_pull_none>, 1318 /* uart2_txm2 */ 1319 <3 RK_PA3 2 &pcfg_pull_none>; 1320 }; 1321 }; 1322 tsadc { 1323 tsadc_otp_gpio: tsadc-otp-gpio { 1324 rockchip,pins = 1325 <0 RK_PA6 0 &pcfg_pull_none>; 1326 }; 1327 1328 tsadc_otp_out: tsadc-otp-out { 1329 rockchip,pins = 1330 <0 RK_PA6 2 &pcfg_pull_none>; 1331 }; 1332 }; 1333 }; 1334}; 1335