// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.

#include <dt-bindings/clock/rk1808-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>

/ {
	compatible = "rockchip,rk1808";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		serial2 = &uart2;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35", "arm,armv8";
			reg = <0x0 0x0>;
			clocks = <&cru ARMCLK>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35", "arm,armv8";
			reg = <0x0 0x1>;
			clocks = <&cru ARMCLK>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>;
	};

	gmac_clkin: external-gmac-clock {
		compatible = "fixed-clock";
		clock-frequency = <125000000>;
		clock-output-names = "gmac_clkin";
		#clock-cells = <0>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
		arm,no-tick-in-suspend;
	};

	xin24m: xin24m {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	xin32k: xin32k {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "xin32k";
		#clock-cells = <0>;
	};

	grf: syscon@fe000000 {
		compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd";
		reg = <0x0 0xfe000000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	pmugrf: syscon@fe410000 {
		compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd";
		reg = <0x0 0xfe410000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	gic: interrupt-controller@ff100000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;

		reg = <0x0 0xff100000 0 0x10000>, /* GICD */
		      <0x0 0xff140000 0 0xc0000>, /* GICR */
		      <0x0 0xff300000 0 0x10000>, /* GICC */
		      <0x0 0xff310000 0 0x10000>, /* GICH */
		      <0x0 0xff320000 0 0x10000>; /* GICV */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		its: interrupt-controller@ff120000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0xff120000 0x0 0x20000>;
		};
	};

	cru: clock-controller@ff350000 {
		compatible = "rockchip,rk1808-cru";
		reg = <0x0 0xff350000 0x0 0x5000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		assigned-clocks =
			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
			<&cru PLL_PPLL>, <&cru ARMCLK>,
			<&cru MSCLK_PERI>, <&cru LSCLK_PERI>,
			<&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>,
			<&cru LSCLK_BUS_PRE>;
		assigned-clock-rates =
			<1200000000>, <1000000000>,
			<416000000>, <816000000>,
			<200000000>, <100000000>,
			<300000000>, <200000000>,
			<100000000>;
	};

	tsadc: tsadc@ff3a0000 {
		compatible = "rockchip,rk1808-tsadc";
		reg = <0x0 0xff3a0000 0x0 0x100>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		rockchip,grf = <&grf>;
		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "tsadc", "apb_pclk";
		assigned-clocks = <&cru SCLK_TSADC>;
		assigned-clock-rates = <50000>;
		resets = <&cru SRST_TSADC>;
		reset-names = "tsadc-apb";
		#thermal-sensor-cells = <1>;
		rockchip,hw-tshut-temp = <120000>;
		status = "disabled";
	};

	pwm0: pwm@ff3d0000 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff3d0000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm0_pin>;
		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm1: pwm@ff3d0010 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff3d0010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm1_pin>;
		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm2: pwm@ff3d0020 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff3d0020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm2_pin>;
		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm3: pwm@ff3d0030 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff3d0030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm3_pin>;
		clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm4: pwm@ff3d8000 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff3d8000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm4_pin>;
		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm5: pwm@ff3d8010 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff3d8010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm5_pin>;
		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm6: pwm@ff3d8020 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff3d8020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm6_pin>;
		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm7: pwm@ff3d8030 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff3d8030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm7_pin>;
		clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	i2c0: i2c@ff410000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff410000 0x0 0x1000>;
		clocks =  <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dmac: dmac@ff4e0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x0 0xff4e0000 0x0 0x4000>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			//clocks = <&cru ACLK_DMAC>;
			//clock-names = "apb_pclk";
			#dma-cells = <1>;
			peripherals-req-type-burst;
		};
	};

	i2c1: i2c@ff500000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff500000 0x0 0x1000>;
		clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@ff504000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff504000 0x0 0x1000>;
		clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2m0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c3: i2c@ff508000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff508000 0x0 0x1000>;
		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c4: i2c@ff50c000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff50c000 0x0 0x1000>;
		clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c5: i2c@ff510000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff100000 0x0 0x1000>;
		clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c5_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi0: spi@ff520000 {
		compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xff520000 0x0 0x1000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac 10>, <&dmac 11>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
		pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>;
		status = "disabled";
	};

	spi1: spi@ff530000 {
		compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xff530000 0x0 0x1000>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac 12>, <&dmac 13>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
		pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>;
		status = "disabled";
	};

	spi2: spi@ff580000 {
		compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xff580000 0x0 0x1000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <&dmac 14>, <&dmac 15>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>;
		pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>;
		status = "disabled";
	};

	uart2: serial@ff550000 {
		compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff550000 0x0 0x100>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	pwm8: pwm@ff5d0000 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff5d0000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm8_pin>;
		clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm9: pwm@fff5d0010 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff5d0010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm9_pin>;
		clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm10: pwm@ff5d0020 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff5d0020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm10_pin>;
		clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	pwm11: pwm@ff5d0030 {
		compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff5d0030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "active";
		pinctrl-0 = <&pwm11_pin>;
		clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
		clock-names = "pwm", "pclk";
		status = "disabled";
	};

	sdmmc: dwmmc@ffcf0000 {
		compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xffcf0000 0x0 0x4000>;
		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
		max-frequency = <150000000>;
		fifo-depth = <0x100>;
		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd>;
		status = "disabled";
	};

	emmc: dwmmc@ffd00000 {
		compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xffd00000 0x0 0x4000>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
		max-frequency = <150000000>;
		fifo-depth = <0x100>;
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	gmac: ethernet@ffdd0000 {
		compatible = "rockchip,rk1808-gmac";
		reg = <0x0 0xffdd0000 0x0 0x10000>;
		rockchip,grf = <&grf>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq";
		clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
			 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>,
			 <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>,
			 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>;
		clock-names = "stmmaceth", "mac_clk_rx",
			      "mac_clk_tx", "clk_mac_ref",
			      "clk_mac_refout", "aclk_mac",
			      "pclk_mac", "clk_mac_speed";
		phy-mode = "rgmii";
		pinctrl-names = "default";
		pinctrl-0 = <&rgmii_pins>;
		resets = <&cru SRST_GAMC_A>;
		reset-names = "stmmaceth";
		/* power-domains = <&power RK1808_PD_GMAC>; */
		status = "disabled";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk1808-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmugrf>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio0: gpio0@ff4c0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff4c0000 0x0 0x100>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru SCLK_PMU_GPIO0>, <&cru PCLK_GPIO0_PMU>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@ff690000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff690000 0x0 0x100>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru SCLK_GPIO1>, <&cru PCLK_GPIO1>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@ff6a0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff6a0000 0x0 0x100>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru SCLK_GPIO2>, <&cru PCLK_GPIO2>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@ff6b0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff6b0000 0x0 0x100>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru SCLK_GPIO3>, <&cru PCLK_GPIO3>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@ff6c0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff6c0000 0x0 0x100>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru SCLK_GPIO4>, <&cru PCLK_GPIO4>;
			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_up: pcfg-pull-up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg-pull-down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg-pull-none {
			bias-disable;
		};

		pcfg_pull_none_2ma: pcfg-pull-none-2ma {
			bias-disable;
			drive-strength = <2>;
		};

		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
			bias-pull-up;
			drive-strength = <2>;
		};

		pcfg_pull_up_4ma: pcfg-pull-up-4ma {
			bias-pull-up;
			drive-strength = <4>;
		};

		pcfg_pull_none_4ma: pcfg-pull-none-4ma {
			bias-disable;
			drive-strength = <4>;
		};

		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
			bias-pull-down;
			drive-strength = <4>;
		};

		pcfg_pull_none_8ma: pcfg-pull-none-8ma {
			bias-disable;
			drive-strength = <8>;
		};

		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
			bias-pull-up;
			drive-strength = <8>;
		};

		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
			bias-disable;
			drive-strength = <12>;
		};

		pcfg_pull_up_12ma: pcfg-pull-up-12ma {
			bias-pull-up;
			drive-strength = <12>;
		};

		pcfg_pull_none_smt: pcfg-pull-none-smt {
			bias-disable;
			input-schmitt-enable;
		};

		pcfg_output_high: pcfg-output-high {
			output-high;
		};

		pcfg_output_low: pcfg-output-low {
			output-low;
		};

		pcfg_input_high: pcfg-input-high {
			bias-pull-up;
			input-enable;
		};

		pcfg_input: pcfg-input {
			input-enable;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins =
					/* emmc_clkout */
					<1 9 1 &pcfg_pull_none>;
			};

			emmc_rstnout: emmc-rstnout {
				rockchip,pins =
					/* emmc_rstn */
					<1 11 1 &pcfg_pull_none>;
			};

			emmc_bus8: emmc-bus8 {
				rockchip,pins =
					/* emmc_d0 */
					<1 RK_PA0 1 &pcfg_pull_none>,
					/* emmc_d1 */
					<1 RK_PA1 1 &pcfg_pull_none>,
					/* emmc_d2 */
					<1 RK_PA2 1 &pcfg_pull_none>,
					/* emmc_d3 */
					<1 RK_PA3 1 &pcfg_pull_none>,
					/* emmc_d4 */
					<1 RK_PA4 1 &pcfg_pull_none>,
					/* emmc_d5 */
					<1 RK_PA5 1 &pcfg_pull_none>,
					/* emmc_d6 */
					<1 RK_PA6 1 &pcfg_pull_none>,
					/* emmc_d7 */
					<1 RK_PA7 1 &pcfg_pull_none>;
			};

			emmc_pwren: emmc-pwren {
				rockchip,pins =
					<1 RK_PB0 1 &pcfg_pull_none>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins =
					<1 RK_PB2 1 &pcfg_pull_none>;
			};
		};

		gmac {
			rgmii_pins: rgmii-pins {
				rockchip,pins =
					/* rgmii_txen */
					<2 RK_PA1 2 &pcfg_pull_none_12ma>,
					/* rgmii_txd1 */
					<2 RK_PA2 2 &pcfg_pull_none_12ma>,
					/* rgmii_txd0 */
					<2 RK_PA3 2 &pcfg_pull_none_12ma>,
					/* rgmii_rxd0 */
					<2 RK_PA4 2 &pcfg_pull_none>,
					/* rgmii_rxd1 */
					<2 RK_PA5 2 &pcfg_pull_none>,
					/* rgmii_rxdv */
					<2 RK_PA7 2 &pcfg_pull_none>,
					/* rgmii_mdio */
					<2 RK_PB0 2 &pcfg_pull_none>,
					/* rgmii_mdc */
					<2 RK_PB2 2 &pcfg_pull_none>,
					/* rgmii_txd3 */
					<2 RK_PB3 2 &pcfg_pull_none_12ma>,
					/* rgmii_txd2 */
					<2 RK_PB4 2 &pcfg_pull_none_12ma>,
					/* rgmii_rxd2 */
					<2 RK_PB5 2 &pcfg_pull_none>,
					/* rgmii_rxd3 */
					<2 RK_PB6 2 &pcfg_pull_none>,
					/* rgmii_clk */
					<2 RK_PB7 2 &pcfg_pull_none>,
					/* rgmii_txclk */
					<2 RK_PC1 2 &pcfg_pull_none_12ma>,
					/* rgmii_rxclk */
					<2 RK_PC2 2 &pcfg_pull_none>;
			};

			rmii_pins: rmii-pins {
				rockchip,pins =
					/* rmii_txen */
					<2 RK_PA1 2 &pcfg_pull_none_12ma>,
					/* rmii_txd1 */
					<2 RK_PA2 2 &pcfg_pull_none_12ma>,
					/* rmii_txd0 */
					<2 RK_PA3 2 &pcfg_pull_none_12ma>,
					/* rmii_rxd0 */
					<2 RK_PA4 2 &pcfg_pull_none>,
					/* rmii_rxd1 */
					<2 RK_PA5 2 &pcfg_pull_none>,
					/* rmii_rxer */
					<2 RK_PA6 2 &pcfg_pull_none>,
					/* rmii_rxdv */
					<2 RK_PA7 2 &pcfg_pull_none>,
					/* rmii_mdio */
					<2 RK_PB0 2 &pcfg_pull_none>,
					/* rmii_mdc */
					<2 RK_PB2 2 &pcfg_pull_none>,
					/* rmii_clk */
					<2 RK_PB7 2 &pcfg_pull_none>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins =
					/* i2c0_sda */
					<0 RK_PB1 1 &pcfg_pull_none_smt>,
					/* i2c0_scl */
					<0 RK_PB0 1 &pcfg_pull_none_smt>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins =
					/* i2c1_sda */
					<0 RK_PC1 1 &pcfg_pull_none_smt>,
					/* i2c1_scl */
					<0 RK_PC0 1 &pcfg_pull_none_smt>;
			};
		};

		i2c2m0 {
			i2c2m0_xfer: i2c2m0-xfer {
				rockchip,pins =
					/* i2c2m0_sda */
					<3 RK_PB4 2 &pcfg_pull_none_smt>,
					/* i2c2m0_scl */
					<3 RK_PB3 2 &pcfg_pull_none_smt>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins =
					/* i2c3_sda */
					<2 RK_PD1 1 &pcfg_pull_none_smt>,
					/* i2c3_scl */
					<2 RK_PD0 1 &pcfg_pull_none_smt>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins =
					/* i2c4_sda */
					<3 RK_PC3 3 &pcfg_pull_none_smt>,
					/* i2c4_scl */
					<3 RK_PC2 3 &pcfg_pull_none_smt>;
			};
		};

		i2c5 {
			i2c5_xfer: i2c5-xfer {
				rockchip,pins =
					/* i2c5_sda */
					<4 RK_PC2 1 &pcfg_pull_none_smt>,
					/* i2c5_scl */
					<4 RK_PC1 1 &pcfg_pull_none_smt>;
			};
		};

		i2s1 {
			i2s1_2ch_lrck: i2s1-2ch-lrck {
				rockchip,pins =
					<3 RK_PA0 1 &pcfg_pull_none>;
			};
			i2s1_2ch_sclk: i2s1-2ch-sclk {
				rockchip,pins =
					<3 RK_PA1 1 &pcfg_pull_none>;
			};
			i2s1_2ch_mclk: i2s1-2ch-mclk {
				rockchip,pins =
					<3 RK_PA2 1 &pcfg_pull_none>;
			};
			i2s1_2ch_sdo: i2s1-2ch-sdo {
				rockchip,pins =
					<3 RK_PA3 1 &pcfg_pull_none>;
			};
			i2s1_2ch_sdi: i2s1-2ch-sdi {
				rockchip,pins =
					<3 RK_PA4 1 &pcfg_pull_none>;
			};
		};

		i2s0 {
			i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
				rockchip,pins =
					<3 RK_PA5 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
				rockchip,pins =
					<3 RK_PA6 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
				rockchip,pins =
					<3 RK_PA7 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
				rockchip,pins =
					<3 RK_PB0 1 &pcfg_pull_none>;
			};
			i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
				rockchip,pins =
					<3 RK_PB1 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
				rockchip,pins =
					<3 RK_PB2 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
				rockchip,pins =
					<3 RK_PB3 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
				rockchip,pins =
					<3 RK_PB4 1 &pcfg_pull_none>;
			};
			i2s0_8ch_mclk: i2s0-8ch-mclk {
				rockchip,pins =
					<3 RK_PB5 1 &pcfg_pull_none>;
			};
			i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
				rockchip,pins =
					<3 RK_PB6 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sclktx: i2s0-8ch-sclktx {
				rockchip,pins =
					<3 RK_PB7 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
				rockchip,pins =
					<3 RK_PC0 1 &pcfg_pull_none>;
			};
			i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
				rockchip,pins =
					<3 RK_PC1 1 &pcfg_pull_none>;
			};
		};

		pciusb {
			pciusb_pins: pciusb-pins {
				rockchip,pins =
					/* pciusb_debug0 */
					<4 RK_PB4 3 &pcfg_pull_none>,
					/* pciusb_debug1 */
					<4 RK_PB5 3 &pcfg_pull_none>,
					/* pciusb_debug2 */
					<4 RK_PB6 3 &pcfg_pull_none>,
					/* pciusb_debug3 */
					<4 RK_PB7 3 &pcfg_pull_none>,
					/* pciusb_debug4 */
					<4 RK_PC0 3 &pcfg_pull_none>,
					/* pciusb_debug5 */
					<4 RK_PC1 3 &pcfg_pull_none>,
					/* pciusb_debug6 */
					<4 RK_PC2 3 &pcfg_pull_none>,
					/* pciusb_debug7 */
					<4 RK_PC3 3 &pcfg_pull_none>;
			};
		};

		pdm {
			pdm_clk: pdm-clk {
				rockchip,pins =
					/* pdm_clk0 */
					<3 RK_PB0 2 &pcfg_pull_none>;
			};

			pdm_sdi3: pdm-sdi3 {
				rockchip,pins =
					<3 RK_PA5 2 &pcfg_pull_none>;
			};

			pdm_sdi2: pdm-sdi2 {
				rockchip,pins =
					<3 RK_PA6 2 &pcfg_pull_none>;
			};

			pdm_sdi1: pdm-sdi1 {
				rockchip,pins =
					<3 RK_PA7 2 &pcfg_pull_none>;
			};

			pdm_clk1: pdm-clk1 {
				rockchip,pins =
					<3 RK_PB1 2 &pcfg_pull_none>;
			};

			pdm_sdi0: pdm-sdi0 {
				rockchip,pins =
					<3 RK_PC1 2 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_pin: pwm0-pin {
				rockchip,pins =
					<0 RK_PB7 1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_pin: pwm1-pin {
				rockchip,pins =
					<0 RK_PC3 1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_pin: pwm2-pin {
				rockchip,pins =
					<0 RK_PC5 1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_pin: pwm3-pin {
				rockchip,pins =
					<0 RK_PC4 1 &pcfg_pull_none>;
			};
		};

		pwm4 {
			pwm4_pin: pwm4-pin {
				rockchip,pins =
					<1 RK_PB6 2 &pcfg_pull_none>;
			};
		};

		pwm5 {
			pwm5_pin: pwm5-pin {
				rockchip,pins =
					<1 RK_PB7 2 &pcfg_pull_none>;
			};
		};
		pwm6 {
			pwm6_pin: pwm6-pin {
				rockchip,pins =
					<3 RK_PA1 2 &pcfg_pull_none>;
			};
		};

		pwm7 {
			pwm7_pin: pwm7-pin {
				rockchip,pins =
					<3 RK_PA2 2 &pcfg_pull_none>;
			};
		};

		pwm8 {
			pwm8_pin: pwm8-pin {
				rockchip,pins =
					<3 RK_PD0 2 &pcfg_pull_none>;
			};
		};

		pwm9 {
			pwm9_pin: pwm9-pin {
				rockchip,pins =
					<3 RK_PD1 2 &pcfg_pull_none>;
			};
		};

		pwm10 {
			pwm10_pin: pwm10-pin {
				rockchip,pins =
					<3 RK_PD2 2 &pcfg_pull_none>;
			};
		};

		pwm11 {
			pwm11_pin: pwm11-pin {
				rockchip,pins =
					<3 RK_PD3 2 &pcfg_pull_none>;
			};
		};

		sdmmc0 {
			sdmmc0_bus4: sdmmc0-bus4 {
				rockchip,pins =
				/* sdmmc0_d0 */
				<4 RK_PA2 1 &pcfg_pull_none>,
				/* sdmmc0_d1 */
				<4 RK_PA3 1 &pcfg_pull_none>,
				/* sdmmc0_d2 */
				<4 RK_PA4 1 &pcfg_pull_none>,
				/* sdmmc0_d3 */
				<4 RK_PA5 1 &pcfg_pull_none>;
			};
			sdmmc0_cmd: sdmmc0-cmd {
				rockchip,pins =
					<4 RK_PA0 1 &pcfg_pull_none>;
			};
			sdmmc0_clk: sdmmc0-clk {
				rockchip,pins =
					<4 RK_PA1 1 &pcfg_pull_none>;
			};
		};

		sdmmc1 {
			sdmmc1_bus4: sdmmc1-bus4 {
				rockchip,pins =
				/* sdmmc1_d0 */
				<4 RK_PB0 1 &pcfg_pull_none>,
				/* sdmmc1_d1 */
				<4 RK_PB1 1 &pcfg_pull_none>,
				/* sdmmc1_d2 */
				<4 RK_PB2 1 &pcfg_pull_none>,
				/* sdmmc1_d3 */
				<4 RK_PB3 1 &pcfg_pull_none>;
			};

			sdmmc1_cmd: sdmmc1-cmd {
				rockchip,pins =
					<4 RK_PA6 1 &pcfg_pull_none>;
			};

			sdmmc1_clk: sdmmc1-clk {
				rockchip,pins =
					<4 RK_PB1 1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_mosi: spi0-mosi {
				rockchip,pins =
					<1 RK_PB4 1 &pcfg_pull_up_4ma>;
			};

			spi0_miso: spi0-miso {
				rockchip,pins =
					<1 RK_PB5 1 &pcfg_pull_up_4ma>;
			};

			spi0_csn: spi0-csn {
				rockchip,pins =
					<1 RK_PB6 1 &pcfg_pull_up_4ma>;
			};

			spi0_clk: spi0-clk {
				rockchip,pins =
					<1 RK_PB7 1 &pcfg_pull_up_4ma>;
			};

			spi0_mosi_hs: spi0-mosi-hs {
				rockchip,pins =
					<1 RK_PB4 1 &pcfg_pull_up_8ma>;
			};

			spi0_miso_hs: spi0-miso-hs {
				rockchip,pins =
					<1 RK_PB5 1 &pcfg_pull_up_8ma>;
			};

			spi0_csn_hs: spi0-csn-hs {
				rockchip,pins =
					<1 RK_PB6 1 &pcfg_pull_up_8ma>;
			};

			spi0_clk_hs: spi0-clk-hs {
				rockchip,pins =
					<1 RK_PB7 1 &pcfg_pull_up_8ma>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins =
					<4 RK_PB4 2 &pcfg_pull_up_4ma>;
			};

			spi1_mosi: spi1-mosi {
				rockchip,pins =
					<4 RK_PB5 2 &pcfg_pull_up_4ma>;
			};

			spi1_csn0: spi1-csn0 {
				rockchip,pins =
					<4 RK_PB6 2 &pcfg_pull_up_4ma>;
			};

			spi1_miso: spi1-miso {
				rockchip,pins =
					<4 RK_PB7 2 &pcfg_pull_up_4ma>;
			};

			spi1_csn1: spi1-csn1 {
				rockchip,pins =
					<4 RK_PC0 2 &pcfg_pull_up_4ma>;
			};

			spi1_clk_hs: spi1-clk-hs {
				rockchip,pins =
					<4 RK_PB4 2 &pcfg_pull_up_8ma>;
			};

			spi1_mosi_hs: spi1-mosi-hs {
				rockchip,pins =
					<4 RK_PB5 2 &pcfg_pull_up_8ma>;
			};

			spi1_csn0_hs: spi1-csn0-hs {
				rockchip,pins =
					<4 RK_PB6 2 &pcfg_pull_up_8ma>;
			};

			spi1_miso_hs: spi1-miso-hs {
				rockchip,pins =
					<4 RK_PB7 2 &pcfg_pull_up_8ma>;
			};

			spi1_csn1_hs: spi1-csn1-hs {
				rockchip,pins =
					<4 RK_PC0 2 &pcfg_pull_up_8ma>;
			};
		};

		spi1m1 {
			spi1m1_clk: spi1m1-clk {
				rockchip,pins =
					<3 RK_PC7 3 &pcfg_pull_up_4ma>;
			};

			spi1m1_mosi: spi1m1-mosi {
				rockchip,pins =
					<3 RK_PD0 3 &pcfg_pull_up_4ma>;
			};

			spi1m1_csn0: spi1m1-csn0 {
				rockchip,pins =
					<3 RK_PD1 3 &pcfg_pull_up_4ma>;
			};

			spi1m1_miso: spi1m1-miso {
				rockchip,pins =
					<3 RK_PD2 3 &pcfg_pull_up_4ma>;
			};

			spi1m1_csn1: spi1m1-csn1 {
				rockchip,pins =
					<3 RK_PD3 3 &pcfg_pull_up_4ma>;
			};

			spi1m1_clk_hs: spi1m1-clk-hs {
				rockchip,pins =
					<3 RK_PC7 3 &pcfg_pull_none>;
			};

			spi1m1_mosi_hs: spi1m1-mosi-hs {
				rockchip,pins =
					<3 RK_PD0 3 &pcfg_pull_none>;
			};

			spi1m1_csn0_hs: spi1m1-csn0-hs {
				rockchip,pins =
					<3 RK_PD1 3 &pcfg_pull_none>;
			};

			spi1m1_miso_hs: spi1m1-miso-hs {
				rockchip,pins =
					<3 RK_PD2 3 &pcfg_pull_none>;
			};

			spi1m1_csn1_hs: spi1m1-csn1-hs {
				rockchip,pins =
					<3 RK_PD3 3 &pcfg_pull_none>;
			};
		};

		spi2m0 {
			spi2m0_miso: spi2m0-miso {
				rockchip,pins =
					<1 RK_PA6 2 &pcfg_pull_up_4ma>;
			};

			spi2m0_clk: spi2m0-clk {
				rockchip,pins =
					<1 RK_PA7 2 &pcfg_pull_up_4ma>;
			};

			spi2m0_mosi: spi2m0-mosi {
				rockchip,pins =
					<1 RK_PB0 2 &pcfg_pull_up_4ma>;
			};

			spi2m0_csn: spi2m0-csn {
				rockchip,pins =
					<1 RK_PB1 2 &pcfg_pull_up_4ma>;
			};

			spi2m0_miso_hs: spi2m0-miso-hs {
				rockchip,pins =
					<1 RK_PA6 2 &pcfg_pull_none>;
			};

			spi2m0_clk_hs: spi2m0-clk-hs {
				rockchip,pins =
					<1 RK_PA7 2 &pcfg_pull_none>;
			};

			spi2m0_mosi_hs: spi2m0-mosi-hs {
				rockchip,pins =
					<1 RK_PB0 2 &pcfg_pull_none>;
			};

			spi2m0_csn_hs: spi2m0-csn-hs {
				rockchip,pins =
					<1 RK_PB1 2 &pcfg_pull_none>;
			};
		};

		spi2m1 {
			spi2m1_miso: spi2m1-miso {
				rockchip,pins =
					<2 RK_PA4 3 &pcfg_pull_up_4ma>;
			};

			spi2m1_clk: spi2m1-clk {
				rockchip,pins =
					<2 RK_PA5 3 &pcfg_pull_up_4ma>;
			};

			spi2m1_mosi: spi2m1-mosi {
				rockchip,pins =
					<2 RK_PA6 3 &pcfg_pull_up_4ma>;
			};

			spi2m1_csn: spi2m1-csn {
				rockchip,pins =
					<2 RK_PA7 3 &pcfg_pull_up_4ma>;
			};

			spi2m1_miso_hs: spi2m1-miso-hs {
				rockchip,pins =
					<2 RK_PA4 3 &pcfg_pull_none>;
			};

			spi2m1_clk_hs: spi2m1-clk-hs {
				rockchip,pins =
					<2 RK_PA5 3 &pcfg_pull_none>;
			};

			spi2m1_mosi_hs: spi2m1-mosi-hs {
				rockchip,pins =
					<2 RK_PA6 3 &pcfg_pull_none>;
			};

			spi2m1_csn_hs: spi2m1-csn-hs {
				rockchip,pins =
					<2 RK_PA7 3 &pcfg_pull_none>;
			};
		};

		uart2m0 {
			uart2m0_xfer: uart2m0-xfer {
				rockchip,pins =
					/* uart2_rxm0 */
					<4 RK_PA3 2 &pcfg_pull_none>,
					/* uart2_txm0 */
					<4 RK_PA2 2 &pcfg_pull_none>;
			};
		};

		uart2m1 {
			uart2m1_xfer: uart2m1-xfer {
				rockchip,pins =
					/* uart2_rxm1 */
					<2 RK_PD1 2 &pcfg_pull_none>,
					/* uart2_txm1 */
					<2 RK_PD0 2 &pcfg_pull_none>;
			};
		};

		uart2m2 {
			uart2m2_xfer: uart2m2-xfer {
				rockchip,pins =
					/* uart2_rxm2 */
					<3 RK_PA4 2 &pcfg_pull_none>,
					/* uart2_txm2 */
					<3 RK_PA3 2 &pcfg_pull_none>;
			};
		};
		tsadc {
			tsadc_otp_gpio: tsadc-otp-gpio {
				rockchip,pins =
					<0 RK_PA6 0 &pcfg_pull_none>;
			};

			tsadc_otp_out: tsadc-otp-out {
				rockchip,pins =
					<0 RK_PA6 2 &pcfg_pull_none>;
			};
		};
	};
};