1menu "ARC architecture" 2 depends on ARC 3 4config SYS_ARCH 5 default "arc" 6 7config SYS_CPU 8 default "arcv1" 9 10choice 11 prompt "CPU selection" 12 default CPU_ARC770D 13 14config CPU_ARC750D 15 bool "ARC 750D" 16 select ARC_MMU_V2 17 help 18 Choose this option to build an U-Boot for ARC750D CPU. 19 20config CPU_ARC770D 21 bool "ARC 770D" 22 select ARC_MMU_V3 23 help 24 Choose this option to build an U-Boot for ARC770D CPU. 25 26endchoice 27 28choice 29 prompt "MMU Version" 30 default ARC_MMU_V3 if CPU_ARC770D 31 default ARC_MMU_V2 if CPU_ARC750D 32 33config ARC_MMU_V2 34 bool "MMU v2" 35 depends on CPU_ARC750D 36 help 37 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio 38 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 39 40config ARC_MMU_V3 41 bool "MMU v3" 42 depends on CPU_ARC770D 43 help 44 Introduced with ARC700 4.10: New Features 45 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 46 Shared Address Spaces (SASID) 47 48endchoice 49 50config SYS_ICACHE_OFF 51 bool "Do not use Instruction Cache" 52 default n 53 54config SYS_DCACHE_OFF 55 bool "Do not use Data Cache" 56 default n 57 58config ARC_CACHE_LINE_SHIFT 59 int "Cache Line Length (as power of 2)" 60 range 5 7 61 default "6" 62 depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF 63 help 64 Starting with ARC700 4.9, Cache line length is configurable, 65 This option specifies "N", with Line-len = 2 power N 66 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 67 Linux only supports same line lengths for I and D caches. 68 69choice 70 prompt "Target select" 71 72config TARGET_TB100 73 bool "Support tb100" 74 75config TARGET_ARCANGEL4 76 bool "Support arcangel4" 77 78config TARGET_ARCANGEL4_BE 79 bool "Support arcangel4-be" 80 81config TARGET_AXS101 82 bool "Support axs101" 83 84endchoice 85 86source "board/abilis/tb100/Kconfig" 87source "board/synopsys/Kconfig" 88source "board/synopsys/axs101/Kconfig" 89 90endmenu 91