1 /* 2 * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include "cpu_errata_info.h" 9 #include <lib/smccc.h> 10 #include <lib/utils_def.h> 11 #include <services/errata_abi_svc.h> 12 #include <smccc_helpers.h> 13 14 /* 15 * Global pointer that points to the specific 16 * structure based on the MIDR part number 17 */ 18 struct em_cpu_list *cpu_ptr; 19 20 extern uint8_t cpu_get_rev_var(void); 21 22 /* Structure array that holds CPU specific errata information */ 23 struct em_cpu_list cpu_list[] = { 24 #if CORTEX_A9_H_INC 25 { 26 .cpu_partnumber = CORTEX_A9_MIDR, 27 .cpu_errata_list = { 28 [0] = {794073, 0x00, 0xFF, ERRATA_A9_794073}, 29 [1 ... ERRATA_LIST_END] = UNDEF_ERRATA, 30 } 31 }, 32 #endif /* CORTEX_A9_H_INC */ 33 34 #if CORTEX_A15_H_INC 35 { 36 .cpu_partnumber = CORTEX_A15_MIDR, 37 .cpu_errata_list = { 38 [0] = {816470, 0x30, 0xFF, ERRATA_A15_816470}, 39 [1] = {827671, 0x30, 0xFF, ERRATA_A15_827671}, 40 [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, 41 } 42 }, 43 #endif /* CORTEX_A15_H_INC */ 44 45 #if CORTEX_A17_H_INC 46 { 47 .cpu_partnumber = CORTEX_A17_MIDR, 48 .cpu_errata_list = { 49 [0] = {852421, 0x00, 0x12, ERRATA_A17_852421}, 50 [1] = {852423, 0x00, 0x12, ERRATA_A17_852423}, 51 [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, 52 } 53 }, 54 #endif /* CORTEX_A17_H_INC */ 55 56 #if CORTEX_A35_H_INC 57 { 58 .cpu_partnumber = CORTEX_A35_MIDR, 59 .cpu_errata_list = { 60 [0] = {855472, 0x00, 0x00, ERRATA_A35_855472}, 61 [1 ... ERRATA_LIST_END] = UNDEF_ERRATA, 62 } 63 }, 64 #endif /* CORTEX_A35_H_INC */ 65 66 #if CORTEX_A53_H_INC 67 { 68 .cpu_partnumber = CORTEX_A53_MIDR, 69 .cpu_errata_list = { 70 [0] = {819472, 0x00, 0x01, ERRATA_A53_819472}, 71 [1] = {824069, 0x00, 0x02, ERRATA_A53_824069}, 72 [2] = {826319, 0x00, 0x02, ERRATA_A53_826319}, 73 [3] = {827319, 0x00, 0x02, ERRATA_A53_827319}, 74 [4] = {835769, 0x00, 0x04, ERRATA_A53_835769}, 75 [5] = {836870, 0x00, 0x03, ERRATA_A53_836870}, 76 [6] = {843419, 0x00, 0x04, ERRATA_A53_843419}, 77 [7] = {855873, 0x03, 0xFF, ERRATA_A53_855873}, 78 [8] = {1530924, 0x00, 0xFF, ERRATA_A53_1530924}, 79 [9 ... ERRATA_LIST_END] = UNDEF_ERRATA, 80 } 81 }, 82 #endif /* CORTEX_A53_H_INC */ 83 84 #if CORTEX_A55_H_INC 85 { 86 .cpu_partnumber = CORTEX_A55_MIDR, 87 .cpu_errata_list = { 88 [0] = {768277, 0x00, 0x00, ERRATA_A55_768277}, 89 [1] = {778703, 0x00, 0x00, ERRATA_A55_778703}, 90 [2] = {798797, 0x00, 0x00, ERRATA_A55_798797}, 91 [3] = {846532, 0x00, 0x01, ERRATA_A55_846532}, 92 [4] = {903758, 0x00, 0x01, ERRATA_A55_903758}, 93 [5] = {1221012, 0x00, 0x10, ERRATA_A55_1221012}, 94 [6] = {1530923, 0x00, 0xFF, ERRATA_A55_1530923}, 95 [7 ... ERRATA_LIST_END] = UNDEF_ERRATA, 96 } 97 }, 98 #endif /* CORTEX_A55_H_INC */ 99 100 #if CORTEX_A57_H_INC 101 { 102 .cpu_partnumber = CORTEX_A57_MIDR, 103 .cpu_errata_list = { 104 [0] = {806969, 0x00, 0x00, ERRATA_A57_806969}, 105 [1] = {813419, 0x00, 0x00, ERRATA_A57_813419}, 106 [2] = {813420, 0x00, 0x00, ERRATA_A57_813420}, 107 [3] = {814670, 0x00, 0x00, ERRATA_A57_814670}, 108 [4] = {817169, 0x00, 0x01, ERRATA_A57_817169}, 109 [5] = {826974, 0x00, 0x11, ERRATA_A57_826974}, 110 [6] = {826977, 0x00, 0x11, ERRATA_A57_826977}, 111 [7] = {828024, 0x00, 0x11, ERRATA_A57_828024}, 112 [8] = {829520, 0x00, 0x12, ERRATA_A57_829520}, 113 [9] = {833471, 0x00, 0x12, ERRATA_A57_833471}, 114 [10] = {859972, 0x00, 0x13, ERRATA_A57_859972}, 115 [11] = {1319537, 0x00, 0xFF, ERRATA_A57_1319537}, 116 [12 ... ERRATA_LIST_END] = UNDEF_ERRATA, 117 } 118 }, 119 #endif /* CORTEX_A57_H_INC */ 120 121 #if CORTEX_A72_H_INC 122 { 123 .cpu_partnumber = CORTEX_A72_MIDR, 124 .cpu_errata_list = { 125 [0] = {859971, 0x00, 0x03, ERRATA_A72_859971}, 126 [1] = {1319367, 0x00, 0xFF, ERRATA_A72_1319367}, 127 [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, 128 } 129 }, 130 #endif /* CORTEX_A72_H_INC */ 131 132 #if CORTEX_A73_H_INC 133 { 134 .cpu_partnumber = CORTEX_A73_MIDR, 135 .cpu_errata_list = { 136 [0] = {852427, 0x00, 0x00, ERRATA_A73_852427}, 137 [1] = {855423, 0x00, 0x01, ERRATA_A73_855423}, 138 [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, 139 } 140 }, 141 #endif /* CORTEX_A73_H_INC */ 142 143 #if CORTEX_A75_H_INC 144 { 145 .cpu_partnumber = CORTEX_A75_MIDR, 146 .cpu_errata_list = { 147 [0] = {764081, 0x00, 0x00, ERRATA_A75_764081}, 148 [1] = {790748, 0x00, 0x00, ERRATA_A75_790748}, 149 [2 ... ERRATA_LIST_END] = UNDEF_ERRATA, 150 } 151 }, 152 #endif /* CORTEX_A75_H_INC */ 153 154 #if CORTEX_A76_H_INC 155 { 156 .cpu_partnumber = CORTEX_A76_MIDR, 157 .cpu_errata_list = { 158 [0] = {1073348, 0x00, 0x10, ERRATA_A76_1073348}, 159 [1] = {1130799, 0x00, 0x20, ERRATA_A76_1130799}, 160 [2] = {1165522, 0x00, 0xFF, ERRATA_A76_1165522}, 161 [3] = {1220197, 0x00, 0x20, ERRATA_A76_1220197}, 162 [4] = {1257314, 0x00, 0x30, ERRATA_A76_1257314}, 163 [5] = {1262606, 0x00, 0x30, ERRATA_A76_1262606}, 164 [6] = {1262888, 0x00, 0x30, ERRATA_A76_1262888}, 165 [7] = {1275112, 0x00, 0x30, ERRATA_A76_1275112}, 166 [8] = {1791580, 0x00, 0x40, ERRATA_A76_1791580}, 167 [9] = {1868343, 0x00, 0x40, ERRATA_A76_1868343}, 168 [10] = {1946160, 0x30, 0x41, ERRATA_A76_1946160}, 169 [11 ... ERRATA_LIST_END] = UNDEF_ERRATA, 170 } 171 }, 172 #endif /* CORTEX_A76_H_INC */ 173 174 #if CORTEX_A77_H_INC 175 { 176 .cpu_partnumber = CORTEX_A77_MIDR, 177 .cpu_errata_list = { 178 [0] = {1508412, 0x00, 0x10, ERRATA_A77_1508412}, 179 [1] = {1791578, 0x00, 0x11, ERRATA_A77_1791578}, 180 [2] = {1800714, 0x00, 0x11, ERRATA_A77_1800714}, 181 [3] = {1925769, 0x00, 0x11, ERRATA_A77_1925769}, 182 [4] = {1946167, 0x00, 0x11, ERRATA_A77_1946167}, 183 [5] = {2356587, 0x00, 0x11, ERRATA_A77_2356587}, 184 [6] = {2743100, 0x00, 0x11, ERRATA_A77_2743100}, 185 [7 ... ERRATA_LIST_END] = UNDEF_ERRATA, 186 } 187 }, 188 #endif /* CORTEX_A77_H_INC */ 189 190 #if CORTEX_A78_H_INC 191 { 192 .cpu_partnumber = CORTEX_A78_MIDR, 193 .cpu_errata_list = { 194 [0] = {1688305, 0x00, 0x10, ERRATA_A78_1688305}, 195 [1] = {1821534, 0x00, 0x10, ERRATA_A78_1821534}, 196 [2] = {1941498, 0x00, 0x11, ERRATA_A78_1941498}, 197 [3] = {1951500, 0x10, 0x11, ERRATA_A78_1951500}, 198 [4] = {1952683, 0x00, 0x00, ERRATA_A78_1952683}, 199 [5] = {2132060, 0x00, 0x12, ERRATA_A78_2132060}, 200 [6] = {2242635, 0x10, 0x12, ERRATA_A78_2242635}, 201 [7] = {2376745, 0x00, 0x12, ERRATA_A78_2376745}, 202 [8] = {2395406, 0x00, 0x12, ERRATA_A78_2395406}, 203 [9] = {2742426, 0x00, 0x12, ERRATA_A78_2742426}, 204 [10] = {2772019, 0x00, 0x12, ERRATA_A78_2772019}, 205 [11] = {2779479, 0x00, 0x12, ERRATA_A78_2779479}, 206 [12 ... ERRATA_LIST_END] = UNDEF_ERRATA, 207 } 208 }, 209 #endif /* CORTEX_A78_H_INC */ 210 211 #if CORTEX_A78_AE_H_INC 212 { 213 .cpu_partnumber = CORTEX_A78_AE_MIDR, 214 .cpu_errata_list = { 215 [0] = {1941500, 0x00, 0x01, ERRATA_A78_AE_1941500}, 216 [1] = {1951502, 0x00, 0x01, ERRATA_A78_AE_1951502}, 217 [2] = {2376748, 0x00, 0x01, ERRATA_A78_AE_2376748}, 218 [3] = {2395408, 0x00, 0x01, ERRATA_A78_AE_2395408}, 219 [4 ... ERRATA_LIST_END] = UNDEF_ERRATA, 220 } 221 }, 222 #endif /* CORTEX_A78_AE_H_INC */ 223 224 #if CORTEX_A78C_H_INC 225 { 226 .cpu_partnumber = CORTEX_A78C_MIDR, 227 .cpu_errata_list = { 228 [0] = {2132064, 0x01, 0x02, ERRATA_A78C_2132064}, 229 [1] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638}, 230 [2] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749}, 231 [3] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411}, 232 [4] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121}, 233 [5] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484}, 234 [6 ... ERRATA_LIST_END] = UNDEF_ERRATA, 235 } 236 }, 237 #endif /* CORTEX_A78C_H_INC */ 238 239 #if CORTEX_X1_H_INC 240 { 241 .cpu_partnumber = CORTEX_X1_MIDR, 242 .cpu_errata_list = { 243 [0] = {1688305, 0x00, 0x10, ERRATA_X1_1688305}, 244 [1] = {1821534, 0x00, 0x10, ERRATA_X1_1821534}, 245 [2] = {1827429, 0x00, 0x10, ERRATA_X1_1827429}, 246 [3 ... ERRATA_LIST_END] = UNDEF_ERRATA, 247 } 248 }, 249 #endif /* CORTEX_X1_H_INC */ 250 251 #if NEOVERSE_N1_H_INC 252 { 253 .cpu_partnumber = NEOVERSE_N1_MIDR, 254 .cpu_errata_list = { 255 [0] = {1073348, 0x00, 0x10, ERRATA_N1_1073348}, 256 [1] = {1130799, 0x00, 0x20, ERRATA_N1_1130799}, 257 [2] = {1165347, 0x00, 0x20, ERRATA_N1_1165347}, 258 [3] = {1207823, 0x00, 0x20, ERRATA_N1_1207823}, 259 [4] = {1220197, 0x00, 0x20, ERRATA_N1_1220197}, 260 [5] = {1257314, 0x00, 0x30, ERRATA_N1_1257314}, 261 [6] = {1262606, 0x00, 0x30, ERRATA_N1_1262606}, 262 [7] = {1262888, 0x00, 0x30, ERRATA_N1_1262888}, 263 [8] = {1275112, 0x00, 0x30, ERRATA_N1_1275112}, 264 [9] = {1315703, 0x00, 0x30, ERRATA_N1_1315703}, 265 [10] = {1542419, 0x30, 0x40, ERRATA_N1_1542419}, 266 [11] = {1868343, 0x00, 0x40, ERRATA_N1_1868343}, 267 [12] = {1946160, 0x30, 0x41, ERRATA_N1_1946160}, 268 [13] = {2743102, 0x00, 0x41, ERRATA_N1_2743102}, 269 [14 ... ERRATA_LIST_END] = UNDEF_ERRATA, 270 } 271 }, 272 #endif /* NEOVERSE_N1_H_INC */ 273 274 #if NEOVERSE_V1_H_INC 275 { 276 .cpu_partnumber = NEOVERSE_V1_MIDR, 277 .cpu_errata_list = { 278 [0] = {1618635, 0x00, 0x0F, ERRATA_V1_1618635}, 279 [1] = {1774420, 0x00, 0x10, ERRATA_V1_1774420}, 280 [2] = {1791573, 0x00, 0x10, ERRATA_V1_1791573}, 281 [3] = {1852267, 0x00, 0x10, ERRATA_V1_1852267}, 282 [4] = {1925756, 0x00, 0x11, ERRATA_V1_1925756}, 283 [5] = {1940577, 0x10, 0x11, ERRATA_V1_1940577}, 284 [6] = {1966096, 0x10, 0x11, ERRATA_V1_1966096}, 285 [7] = {2108267, 0x00, 0x11, ERRATA_V1_2108267}, 286 [8] = {2139242, 0x00, 0x11, ERRATA_V1_2139242}, 287 [9] = {2216392, 0x10, 0x11, ERRATA_V1_2216392}, 288 [10] = {2294912, 0x00, 0x11, ERRATA_V1_2294912}, 289 [11] = {2372203, 0x00, 0x11, ERRATA_V1_2372203}, 290 [12] = {2743093, 0x00, 0x12, ERRATA_V1_2743093}, 291 [13] = {2779461, 0x00, 0x12, ERRATA_V1_2779461}, 292 [14 ... ERRATA_LIST_END] = UNDEF_ERRATA, 293 } 294 }, 295 #endif /* NEOVERSE_V1_H_INC */ 296 297 #if CORTEX_A710_H_INC 298 { 299 .cpu_partnumber = CORTEX_A710_MIDR, 300 .cpu_errata_list = { 301 [0] = {1987031, 0x00, 0x20, ERRATA_A710_1987031}, 302 [1] = {2008768, 0x00, 0x20, ERRATA_A710_2008768}, 303 [2] = {2017096, 0x00, 0x20, ERRATA_A710_2017096}, 304 [3] = {2055002, 0x10, 0x20, ERRATA_A710_2055002}, 305 [4] = {2058056, 0x00, 0x10, ERRATA_A710_2058056}, 306 [5] = {2081180, 0x00, 0x20, ERRATA_A710_2081180}, 307 [6] = {2083908, 0x20, 0x20, ERRATA_A710_2083908}, 308 [7] = {2136059, 0x00, 0x20, ERRATA_A710_2136059}, 309 [8] = {2147715, 0x20, 0x20, ERRATA_A710_2147715}, 310 [9] = {2216384, 0x00, 0x20, ERRATA_A710_2216384}, 311 [10] = {2267065, 0x00, 0x20, ERRATA_A710_2267065}, 312 [11] = {2282622, 0x00, 0x21, ERRATA_A710_2282622}, 313 [12] = {2291219, 0x00, 0x20, ERRATA_A710_2291219}, 314 [13] = {2371105, 0x00, 0x20, ERRATA_A710_2371105}, 315 [14] = {2768515, 0x00, 0x21, ERRATA_A710_2768515} 316 } 317 }, 318 #endif /* CORTEX_A710_H_INC */ 319 320 #if NEOVERSE_N2_H_INC 321 { 322 .cpu_partnumber = NEOVERSE_N2_MIDR, 323 .cpu_errata_list = { 324 [0] = {2002655, 0x00, 0x00, ERRATA_N2_2002655}, 325 [1] = {2025414, 0x00, 0x00, ERRATA_N2_2025414}, 326 [2] = {2067956, 0x00, 0x00, ERRATA_N2_2067956}, 327 [3] = {2138953, 0x00, 0x00, ERRATA_N2_2138953}, 328 [4] = {2138956, 0x00, 0x00, ERRATA_N2_2138956}, 329 [5] = {2138958, 0x00, 0x00, ERRATA_N2_2138958}, 330 [6] = {2189731, 0x00, 0x00, ERRATA_N2_2189731}, 331 [7] = {2242400, 0x00, 0x00, ERRATA_N2_2242400}, 332 [8] = {2242415, 0x00, 0x00, ERRATA_N2_2242415}, 333 [9] = {2280757, 0x00, 0x00, ERRATA_N2_2280757}, 334 [10] = {2326639, 0x00, 0x00, ERRATA_N2_2326639}, 335 [11] = {2376738, 0x00, 0x00, ERRATA_N2_2376738}, 336 [12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450}, 337 [13] = {2743089, 0x00, 0x02, ERRATA_N2_2743089}, 338 [14 ... ERRATA_LIST_END] = UNDEF_ERRATA, 339 } 340 }, 341 #endif /* NEOVERSE_N2_H_INC */ 342 343 #if CORTEX_X2_H_INC 344 { 345 .cpu_partnumber = CORTEX_X2_MIDR, 346 .cpu_errata_list = { 347 [0] = {2002765, 0x00, 0x20, ERRATA_X2_2002765}, 348 [1] = {2017096, 0x00, 0x20, ERRATA_X2_2017096}, 349 [2] = {2058056, 0x00, 0x20, ERRATA_X2_2058056}, 350 [3] = {2081180, 0x00, 0x20, ERRATA_X2_2081180}, 351 [4] = {2083908, 0x00, 0x20, ERRATA_X2_2083908}, 352 [5] = {2147715, 0x20, 0x20, ERRATA_X2_2147715}, 353 [6] = {2216384, 0x00, 0x20, ERRATA_X2_2216384}, 354 [7] = {2282622, 0x00, 0x21, ERRATA_X2_2282622}, 355 [8] = {2371105, 0x00, 0x21, ERRATA_X2_2371105}, 356 [9] = {2768515, 0x00, 0x21, ERRATA_X2_2768515}, 357 [10 ... ERRATA_LIST_END] = UNDEF_ERRATA, 358 } 359 }, 360 #endif /* CORTEX_X2_H_INC */ 361 362 #if CORTEX_A510_H_INC 363 { 364 .cpu_partnumber = CORTEX_A510_MIDR, 365 .cpu_errata_list = { 366 [0] = {1922240, 0x00, 0x00, ERRATA_A510_1922240}, 367 [1] = {2041909, 0x02, 0x02, ERRATA_A510_2041909}, 368 [2] = {2042739, 0x00, 0x02, ERRATA_A510_2042739}, 369 [3] = {2172148, 0x00, 0x10, ERRATA_A510_2172148}, 370 [4] = {2218950, 0x00, 0x10, ERRATA_A510_2218950}, 371 [5] = {2250311, 0x00, 0x10, ERRATA_A510_2250311}, 372 [6] = {2288014, 0x00, 0x10, ERRATA_A510_2288014}, 373 [7] = {2347730, 0x00, 0x11, ERRATA_A510_2347730}, 374 [8] = {2371937, 0x00, 0x11, ERRATA_A510_2371937}, 375 [9] = {2666669, 0x00, 0x11, ERRATA_A510_2666669}, 376 [10] = {2684597, 0x00, 0x12, ERRATA_A510_2684597}, 377 [11 ... ERRATA_LIST_END] = UNDEF_ERRATA, 378 } 379 }, 380 #endif /* CORTEX_A510_H_INC */ 381 }; 382 383 /* 384 * Function to do binary search and check for the specific errata ID 385 * in the array of structures specific to the cpu identified. 386 */ 387 int32_t binary_search(struct em_cpu_list *ptr, uint32_t erratum_id, 388 uint8_t rxpx_val) 389 { 390 int low_index = 0U, mid_index = 0U; 391 392 int high_index = MAX_ERRATA_ENTRIES - 1; 393 394 while (low_index <= high_index) { 395 mid_index = (low_index + high_index) / 2; 396 if (erratum_id < ptr->cpu_errata_list[mid_index].em_errata_id) { 397 high_index = mid_index - 1; 398 } else if (erratum_id > ptr->cpu_errata_list[mid_index].em_errata_id) { 399 low_index = mid_index + 1; 400 } else if (erratum_id == ptr->cpu_errata_list[mid_index].em_errata_id) { 401 402 if (RXPX_RANGE(rxpx_val, ptr->cpu_errata_list[mid_index].em_rxpx_lo, \ 403 ptr->cpu_errata_list[mid_index].em_rxpx_hi)) { 404 if (ptr->cpu_errata_list[mid_index].errata_enabled) { 405 return EM_HIGHER_EL_MITIGATION; 406 } 407 return EM_AFFECTED; 408 } 409 return EM_NOT_AFFECTED; 410 } 411 } 412 /* no matching errata ID */ 413 return EM_UNKNOWN_ERRATUM; 414 } 415 416 /* Function to check if the errata exists for the specific CPU and rxpx */ 417 int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag) 418 { 419 /* 420 * Read MIDR value and extract the revision, variant and partnumber 421 */ 422 static uint32_t midr_val, cpu_partnum; 423 static uint8_t cpu_rxpx_val; 424 int32_t ret_val = EM_UNKNOWN_ERRATUM; 425 426 /* Determine the number of cpu listed in the cpu list */ 427 uint8_t size_cpulist = ARRAY_SIZE(cpu_list); 428 429 /* Read the midr reg to extract cpu, revision and variant info */ 430 midr_val = read_midr(); 431 432 /* Extract revision and variant from the MIDR register */ 433 cpu_rxpx_val = cpu_get_rev_var(); 434 435 /* Extract the cpu partnumber and check if the cpu is in the cpu list */ 436 cpu_partnum = EXTRACT_PARTNUM(midr_val); 437 438 for (uint8_t i = 0; i < size_cpulist; i++) { 439 cpu_ptr = &cpu_list[i]; 440 uint16_t partnum_extracted = EXTRACT_PARTNUM(cpu_ptr->cpu_partnumber); 441 442 if (partnum_extracted == cpu_partnum) { 443 /* 444 * If the midr value is in the cpu list, binary search 445 * for the errata ID and specific revision in the list. 446 */ 447 ret_val = binary_search(cpu_ptr, errata_id, cpu_rxpx_val); 448 break; 449 } 450 } 451 return ret_val; 452 } 453 454 /* Predicate indicating that a function id is part of EM_ABI */ 455 bool is_errata_fid(uint32_t smc_fid) 456 { 457 return ((smc_fid == ARM_EM_VERSION) || 458 (smc_fid == ARM_EM_FEATURES) || 459 (smc_fid == ARM_EM_CPU_ERRATUM_FEATURES)); 460 461 } 462 463 bool validate_spsr_mode(void) 464 { 465 /* In AArch64, if the caller is EL1, return true */ 466 467 #if __aarch64__ 468 if (GET_EL(read_spsr_el3()) == MODE_EL1) { 469 return true; 470 } 471 return false; 472 #else 473 474 /* In AArch32, if in system/svc mode, return true */ 475 uint8_t read_el_state = GET_M32(read_spsr()); 476 477 if ((read_el_state == (MODE32_svc)) || (read_el_state == MODE32_sys)) { 478 return true; 479 } 480 return false; 481 #endif /* __aarch64__ */ 482 } 483 484 uintptr_t errata_abi_smc_handler(uint32_t smc_fid, u_register_t x1, 485 u_register_t x2, u_register_t x3, u_register_t x4, 486 void *cookie, void *handle, u_register_t flags) 487 { 488 int32_t ret_id = EM_UNKNOWN_ERRATUM; 489 490 switch (smc_fid) { 491 case ARM_EM_VERSION: 492 SMC_RET1(handle, MAKE_SMCCC_VERSION( 493 EM_VERSION_MAJOR, EM_VERSION_MINOR 494 )); 495 break; /* unreachable */ 496 case ARM_EM_FEATURES: 497 if (is_errata_fid((uint32_t)x1)) { 498 SMC_RET1(handle, EM_SUCCESS); 499 } 500 501 SMC_RET1(handle, EM_NOT_SUPPORTED); 502 break; /* unreachable */ 503 case ARM_EM_CPU_ERRATUM_FEATURES: 504 505 /* 506 * If the forward flag is greater than zero and the calling EL 507 * is EL1 in AArch64 or in system mode or svc mode in case of AArch32, 508 * return Invalid Parameters. 509 */ 510 if (((uint32_t)x2 != 0) && (validate_spsr_mode())) { 511 SMC_RET1(handle, EM_INVALID_PARAMETERS); 512 } 513 ret_id = verify_errata_implemented((uint32_t)x1, (uint32_t)x2); 514 SMC_RET1(handle, ret_id); 515 break; /* unreachable */ 516 default: 517 { 518 WARN("Unimplemented Errata ABI Service Call: 0x%x\n", smc_fid); 519 SMC_RET1(handle, EM_UNKNOWN_ERRATUM); 520 break; /* unreachable */ 521 } 522 } 523 } 524