1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * ZynqMP system level PM-API functions for pin control. 9 */ 10 11 #ifndef _PM_API_IOCTL_H_ 12 #define _PM_API_IOCTL_H_ 13 14 #include "pm_common.h" 15 16 //ioctl id 17 enum { 18 IOCTL_GET_RPU_OPER_MODE, 19 IOCTL_SET_RPU_OPER_MODE, 20 IOCTL_RPU_BOOT_ADDR_CONFIG, 21 IOCTL_TCM_COMB_CONFIG, 22 IOCTL_SET_TAPDELAY_BYPASS, 23 IOCTL_SET_SGMII_MODE, 24 IOCTL_SD_DLL_RESET, 25 IOCTL_SET_SD_TAPDELAY, 26 /* Ioctl for clock driver */ 27 IOCTL_SET_PLL_FRAC_MODE, 28 IOCTL_GET_PLL_FRAC_MODE, 29 IOCTL_SET_PLL_FRAC_DATA, 30 IOCTL_GET_PLL_FRAC_DATA, 31 IOCTL_WRITE_GGS, 32 IOCTL_READ_GGS, 33 IOCTL_WRITE_PGGS, 34 IOCTL_READ_PGGS, 35 }; 36 37 //RPU operation mode 38 #define PM_RPU_MODE_LOCKSTEP 0U 39 #define PM_RPU_MODE_SPLIT 1U 40 41 //RPU boot mem 42 #define PM_RPU_BOOTMEM_LOVEC 0U 43 #define PM_RPU_BOOTMEM_HIVEC 1U 44 45 //RPU tcm mpde 46 #define PM_RPU_TCM_SPLIT 0U 47 #define PM_RPU_TCM_COMB 1U 48 49 //tap delay signal type 50 #define PM_TAPDELAY_NAND_DQS_IN 0U 51 #define PM_TAPDELAY_NAND_DQS_OUT 1U 52 #define PM_TAPDELAY_QSPI 2U 53 #define PM_TAPDELAY_MAX 3U 54 55 //tap delay bypass 56 #define PM_TAPDELAY_BYPASS_DISABLE 0U 57 #define PM_TAPDELAY_BYPASS_ENABLE 1U 58 59 //sgmii mode 60 #define PM_SGMII_DISABLE 0U 61 #define PM_SGMII_ENABLE 1U 62 63 enum tap_delay_type { 64 PM_TAPDELAY_INPUT, 65 PM_TAPDELAY_OUTPUT, 66 }; 67 68 //dll reset type 69 #define PM_DLL_RESET_ASSERT 0U 70 #define PM_DLL_RESET_RELEASE 1U 71 #define PM_DLL_RESET_PULSE 2U 72 73 enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, 74 unsigned int ioctl_id, 75 unsigned int arg1, 76 unsigned int arg2, 77 unsigned int *value); 78 #endif /* _PM_API_IOCTL_H_ */ 79