1 /* 2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * ZynqMP system level PM-API functions for pin control. 10 */ 11 12 #ifndef PM_API_IOCTL_H 13 #define PM_API_IOCTL_H 14 15 #include "pm_common.h" 16 17 //RPU operation mode 18 #define PM_RPU_MODE_LOCKSTEP 0U 19 #define PM_RPU_MODE_SPLIT 1U 20 21 //RPU boot mem 22 #define PM_RPU_BOOTMEM_LOVEC 0U 23 #define PM_RPU_BOOTMEM_HIVEC 1U 24 25 //RPU tcm mpde 26 #define PM_RPU_TCM_SPLIT 0U 27 #define PM_RPU_TCM_COMB 1U 28 29 //tap delay signal type 30 #define PM_TAPDELAY_NAND_DQS_IN 0U 31 #define PM_TAPDELAY_NAND_DQS_OUT 1U 32 #define PM_TAPDELAY_QSPI 2U 33 #define PM_TAPDELAY_MAX 3U 34 35 //tap delay bypass 36 #define PM_TAPDELAY_BYPASS_DISABLE 0U 37 #define PM_TAPDELAY_BYPASS_ENABLE 1U 38 39 //sgmii mode 40 #define PM_SGMII_DISABLE 0U 41 #define PM_SGMII_ENABLE 1U 42 43 enum tap_delay_type { 44 PM_TAPDELAY_INPUT, 45 PM_TAPDELAY_OUTPUT, 46 }; 47 48 //dll reset type 49 #define PM_DLL_RESET_ASSERT 0U 50 #define PM_DLL_RESET_RELEASE 1U 51 #define PM_DLL_RESET_PULSE 2U 52 53 enum pm_ret_status pm_api_ioctl(enum pm_node_id nid, 54 uint32_t ioctl_id, 55 uint32_t arg1, 56 uint32_t arg2, 57 uint32_t *value); 58 enum pm_ret_status atf_ioctl_bitmask(uint32_t *bit_mask); 59 #endif /* PM_API_IOCTL_H */ 60