1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/arm/gicv2.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/common/platform.h> 17 18 #include <plat_private.h> 19 #include "pm_api_sys.h" 20 #include "pm_client.h" 21 22 uintptr_t zynqmp_sec_entry; 23 24 void zynqmp_cpu_standby(plat_local_state_t cpu_state) 25 { 26 VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); 27 28 dsb(); 29 wfi(); 30 } 31 32 static int zynqmp_pwr_domain_on(u_register_t mpidr) 33 { 34 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); 35 const struct pm_proc *proc; 36 37 VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); 38 39 if (cpu_id == -1) 40 return PSCI_E_INTERN_FAIL; 41 42 proc = pm_get_proc(cpu_id); 43 /* Clear power down request */ 44 pm_client_wakeup(proc); 45 46 /* Send request to PMU to wake up selected APU CPU core */ 47 pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING); 48 49 return PSCI_E_SUCCESS; 50 } 51 52 static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) 53 { 54 unsigned int cpu_id = plat_my_core_pos(); 55 const struct pm_proc *proc = pm_get_proc(cpu_id); 56 57 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 58 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 59 __func__, i, target_state->pwr_domain_state[i]); 60 61 /* Prevent interrupts from spuriously waking up this cpu */ 62 gicv2_cpuif_disable(); 63 64 /* 65 * Send request to PMU to power down the appropriate APU CPU 66 * core. 67 * According to PSCI specification, CPU_off function does not 68 * have resume address and CPU core can only be woken up 69 * invoking CPU_on function, during which resume address will 70 * be set. 71 */ 72 pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0); 73 } 74 75 static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) 76 { 77 unsigned int state; 78 unsigned int cpu_id = plat_my_core_pos(); 79 const struct pm_proc *proc = pm_get_proc(cpu_id); 80 81 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 82 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 83 __func__, i, target_state->pwr_domain_state[i]); 84 85 state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? 86 PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; 87 88 /* Send request to PMU to suspend this core */ 89 pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry); 90 91 /* APU is to be turned off */ 92 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 93 /* disable coherency */ 94 plat_arm_interconnect_exit_coherency(); 95 } 96 } 97 98 static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) 99 { 100 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 101 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 102 __func__, i, target_state->pwr_domain_state[i]); 103 plat_arm_gic_pcpu_init(); 104 gicv2_cpuif_enable(); 105 } 106 107 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 108 { 109 unsigned int cpu_id = plat_my_core_pos(); 110 const struct pm_proc *proc = pm_get_proc(cpu_id); 111 112 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) 113 VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", 114 __func__, i, target_state->pwr_domain_state[i]); 115 116 /* Clear the APU power control register for this cpu */ 117 pm_client_wakeup(proc); 118 119 /* enable coherency */ 120 plat_arm_interconnect_enter_coherency(); 121 /* APU was turned off */ 122 if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { 123 plat_arm_gic_init(); 124 } else { 125 gicv2_cpuif_enable(); 126 gicv2_pcpu_distif_init(); 127 } 128 } 129 130 /******************************************************************************* 131 * ZynqMP handlers to shutdown/reboot the system 132 ******************************************************************************/ 133 134 static void __dead2 zynqmp_system_off(void) 135 { 136 /* disable coherency */ 137 plat_arm_interconnect_exit_coherency(); 138 139 /* Send the power down request to the PMU */ 140 pm_system_shutdown(PMF_SHUTDOWN_TYPE_SHUTDOWN, 141 pm_get_shutdown_scope()); 142 143 while (1) 144 wfi(); 145 } 146 147 static void __dead2 zynqmp_system_reset(void) 148 { 149 /* disable coherency */ 150 plat_arm_interconnect_exit_coherency(); 151 152 /* Send the system reset request to the PMU */ 153 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, 154 pm_get_shutdown_scope()); 155 156 while (1) 157 wfi(); 158 } 159 160 int zynqmp_validate_power_state(unsigned int power_state, 161 psci_power_state_t *req_state) 162 { 163 VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); 164 165 int pstate = psci_get_pstate_type(power_state); 166 167 assert(req_state); 168 169 /* Sanity check the requested state */ 170 if (pstate == PSTATE_TYPE_STANDBY) 171 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; 172 else 173 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 174 175 /* We expect the 'state id' to be zero */ 176 if (psci_get_pstate_id(power_state)) 177 return PSCI_E_INVALID_PARAMS; 178 179 return PSCI_E_SUCCESS; 180 } 181 182 int zynqmp_validate_ns_entrypoint(unsigned long ns_entrypoint) 183 { 184 VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint); 185 186 /* FIXME: Actually validate */ 187 return PSCI_E_SUCCESS; 188 } 189 190 void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) 191 { 192 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; 193 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; 194 } 195 196 /******************************************************************************* 197 * Export the platform handlers to enable psci to invoke them 198 ******************************************************************************/ 199 static const struct plat_psci_ops zynqmp_psci_ops = { 200 .cpu_standby = zynqmp_cpu_standby, 201 .pwr_domain_on = zynqmp_pwr_domain_on, 202 .pwr_domain_off = zynqmp_pwr_domain_off, 203 .pwr_domain_suspend = zynqmp_pwr_domain_suspend, 204 .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, 205 .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, 206 .system_off = zynqmp_system_off, 207 .system_reset = zynqmp_system_reset, 208 .validate_power_state = zynqmp_validate_power_state, 209 .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, 210 .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, 211 }; 212 213 /******************************************************************************* 214 * Export the platform specific power ops. 215 ******************************************************************************/ 216 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 217 const struct plat_psci_ops **psci_ops) 218 { 219 zynqmp_sec_entry = sec_entrypoint; 220 221 *psci_ops = &zynqmp_psci_ops; 222 223 return 0; 224 } 225