1 /* 2 * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 15 #include "zynqmp_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #define PLATFORM_STACK_SIZE 0x440 23 24 #define PLATFORM_CORE_COUNT U(4) 25 #define PLAT_NUM_POWER_DOMAINS U(5) 26 #define PLAT_MAX_PWR_LVL U(1) 27 #define PLAT_MAX_RET_STATE U(1) 28 #define PLAT_MAX_OFF_STATE U(2) 29 30 /******************************************************************************* 31 * BL31 specific defines. 32 ******************************************************************************/ 33 /* 34 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 35 * present). BL31_BASE is calculated using the current BL31 debug size plus a 36 * little space for growth. 37 */ 38 #ifndef ZYNQMP_ATF_MEM_BASE 39 #if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT 40 # define BL31_BASE U(0xfffea000) 41 # define BL31_LIMIT U(0x100000000) 42 #else 43 # define BL31_BASE U(0x1000) 44 # define BL31_LIMIT U(0x7ffff) 45 #endif 46 #else 47 # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 48 # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 49 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 50 # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 51 # endif 52 #endif 53 54 /******************************************************************************* 55 * BL32 specific defines. 56 ******************************************************************************/ 57 #ifndef ZYNQMP_BL32_MEM_BASE 58 # define BL32_BASE U(0x60000000) 59 # define BL32_LIMIT U(0x7fffffff) 60 #else 61 # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 62 # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 63 #endif 64 65 /******************************************************************************* 66 * BL33 specific defines. 67 ******************************************************************************/ 68 #ifndef PRELOADED_BL33_BASE 69 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 70 #else 71 # define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE 72 #endif 73 74 /******************************************************************************* 75 * TSP specific defines. 76 ******************************************************************************/ 77 #define TSP_SEC_MEM_BASE BL32_BASE 78 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 79 80 /* ID of the secure physical generic timer interrupt used by the TSP */ 81 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 82 83 /******************************************************************************* 84 * Platform specific page table and MMU setup constants 85 ******************************************************************************/ 86 #define XILINX_OF_BOARD_DTB_ADDR U(0x100000) 87 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 88 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 89 90 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 91 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 92 93 #ifndef MAX_MMAP_REGIONS 94 #if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) 95 #define MAX_MMAP_REGIONS 8 96 #else 97 #define MAX_MMAP_REGIONS 7 98 #endif 99 #endif 100 101 #ifndef MAX_XLAT_TABLES 102 #if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX) 103 #define MAX_XLAT_TABLES 8 104 #else 105 #define MAX_XLAT_TABLES 5 106 #endif 107 #endif 108 109 #define CACHE_WRITEBACK_SHIFT 6 110 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 111 112 #define ZYNQMP_SDEI_SGI_PRIVATE U(8) 113 114 /* Platform macros to support exception handling framework */ 115 #define PLAT_PRI_BITS U(3) 116 #define PLAT_SDEI_CRITICAL_PRI 0x10 117 #define PLAT_SDEI_NORMAL_PRI 0x20 118 119 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 120 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 121 /* 122 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 123 * terminology. On a GICv2 system or mode, the lists will be merged and treated 124 * as Group 0 interrupts. 125 */ 126 #if !ZYNQMP_WDT_RESTART 127 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 128 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 129 GIC_INTR_CFG_LEVEL), \ 130 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 131 GIC_INTR_CFG_EDGE), \ 132 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 133 GIC_INTR_CFG_EDGE), \ 134 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 135 GIC_INTR_CFG_EDGE), \ 136 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_EDGE), \ 138 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 139 GIC_INTR_CFG_EDGE), \ 140 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 141 GIC_INTR_CFG_EDGE), \ 142 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 143 GIC_INTR_CFG_EDGE) 144 #else 145 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 146 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 147 GIC_INTR_CFG_LEVEL), \ 148 INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 149 GIC_INTR_CFG_EDGE), \ 150 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 151 GIC_INTR_CFG_EDGE), \ 152 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 153 GIC_INTR_CFG_EDGE), \ 154 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 155 GIC_INTR_CFG_EDGE), \ 156 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 157 GIC_INTR_CFG_EDGE), \ 158 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 159 GIC_INTR_CFG_EDGE), \ 160 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 161 GIC_INTR_CFG_EDGE), \ 162 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 163 GIC_INTR_CFG_EDGE) 164 #endif 165 166 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 167 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ 168 GIC_INTR_CFG_EDGE) 169 170 #endif /* PLATFORM_DEF_H */ 171