1 /* 2 * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic_common.h> 15 #include <lib/utils_def.h> 16 17 #include "zynqmp_def.h" 18 19 /******************************************************************************* 20 * Generic platform constants 21 ******************************************************************************/ 22 23 /* Size of cacheable stacks */ 24 #define PLATFORM_STACK_SIZE 0x440 25 26 #define PLATFORM_CORE_COUNT U(4) 27 #define PLAT_NUM_POWER_DOMAINS U(5) 28 #define PLAT_MAX_PWR_LVL U(1) 29 #define PLAT_MAX_RET_STATE U(1) 30 #define PLAT_MAX_OFF_STATE U(2) 31 32 /******************************************************************************* 33 * BL31 specific defines. 34 ******************************************************************************/ 35 /* 36 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 37 * present). BL31_BASE is calculated using the current BL31 debug size plus a 38 * little space for growth. 39 */ 40 #ifndef ZYNQMP_ATF_MEM_BASE 41 #if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT 42 # define BL31_BASE U(0xfffea000) 43 # define BL31_LIMIT U(0x100000000) 44 #else 45 # define BL31_BASE U(0x1000) 46 # define BL31_LIMIT U(0x7ffff) 47 #endif 48 #else 49 # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 50 # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 51 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 52 # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 53 # endif 54 #endif 55 56 /******************************************************************************* 57 * BL32 specific defines. 58 ******************************************************************************/ 59 #ifndef ZYNQMP_BL32_MEM_BASE 60 # define BL32_BASE U(0x60000000) 61 # define BL32_LIMIT U(0x7fffffff) 62 #else 63 # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 64 # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 65 #endif 66 67 /******************************************************************************* 68 * BL33 specific defines. 69 ******************************************************************************/ 70 #ifndef PRELOADED_BL33_BASE 71 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 72 #else 73 # define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE 74 #endif 75 76 /******************************************************************************* 77 * TSP specific defines. 78 ******************************************************************************/ 79 #define TSP_SEC_MEM_BASE BL32_BASE 80 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 81 82 /* ID of the secure physical generic timer interrupt used by the TSP */ 83 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 84 85 /******************************************************************************* 86 * Platform specific page table and MMU setup constants 87 ******************************************************************************/ 88 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 89 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 90 #define PLAT_OCM_BASE U(0xFFFC0000) 91 #define PLAT_OCM_LIMIT U(0xFFFFFFFF) 92 93 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 94 95 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 96 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 97 98 #ifndef MAX_MMAP_REGIONS 99 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 100 #define MAX_MMAP_REGIONS 8 101 #else 102 #define MAX_MMAP_REGIONS 7 103 #endif 104 #endif 105 106 #ifndef MAX_XLAT_TABLES 107 #if !IS_TFA_IN_OCM(BL31_BASE) 108 #define MAX_XLAT_TABLES 8 109 #else 110 #define MAX_XLAT_TABLES 5 111 #endif 112 #endif 113 114 #define CACHE_WRITEBACK_SHIFT 6 115 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 116 117 #define ZYNQMP_SDEI_SGI_PRIVATE U(8) 118 119 /* Platform macros to support exception handling framework */ 120 #define PLAT_PRI_BITS U(3) 121 #define PLAT_SDEI_CRITICAL_PRI 0x10 122 #define PLAT_SDEI_NORMAL_PRI 0x20 123 124 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 125 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 126 /* 127 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 128 * terminology. On a GICv2 system or mode, the lists will be merged and treated 129 * as Group 0 interrupts. 130 */ 131 #if !ZYNQMP_WDT_RESTART 132 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 133 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 134 GIC_INTR_CFG_LEVEL), \ 135 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 136 GIC_INTR_CFG_EDGE), \ 137 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 138 GIC_INTR_CFG_EDGE), \ 139 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 140 GIC_INTR_CFG_EDGE), \ 141 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 142 GIC_INTR_CFG_EDGE), \ 143 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 144 GIC_INTR_CFG_EDGE), \ 145 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 146 GIC_INTR_CFG_EDGE), \ 147 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 148 GIC_INTR_CFG_EDGE) 149 #else 150 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 151 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 152 GIC_INTR_CFG_LEVEL), \ 153 INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 154 GIC_INTR_CFG_EDGE), \ 155 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 156 GIC_INTR_CFG_EDGE), \ 157 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 158 GIC_INTR_CFG_EDGE), \ 159 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 160 GIC_INTR_CFG_EDGE), \ 161 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 162 GIC_INTR_CFG_EDGE), \ 163 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 164 GIC_INTR_CFG_EDGE), \ 165 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 166 GIC_INTR_CFG_EDGE), \ 167 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 168 GIC_INTR_CFG_EDGE) 169 #endif 170 171 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 172 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ 173 GIC_INTR_CFG_EDGE) 174 175 #endif /* PLATFORM_DEF_H */ 176