1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arch.h> 35 #include "../zynqmp_def.h" 36 37 /******************************************************************************* 38 * Generic platform constants 39 ******************************************************************************/ 40 41 /* Size of cacheable stacks */ 42 #define PLATFORM_STACK_SIZE 0x440 43 44 #define PLATFORM_CORE_COUNT 4 45 #define PLAT_NUM_POWER_DOMAINS 5 46 #define PLAT_MAX_PWR_LVL 1 47 #define PLAT_MAX_RET_STATE 1 48 #define PLAT_MAX_OFF_STATE 2 49 50 /******************************************************************************* 51 * BL31 specific defines. 52 ******************************************************************************/ 53 54 #define ZYNQMP_BL31_SIZE 0x1b000 55 /* 56 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 57 * present). BL31_BASE is calculated using the current BL31 debug size plus a 58 * little space for growth. 59 */ 60 #if ZYNQMP_ATF_LOCATION_ID == ZYNQMP_IN_TRUSTED_SRAM 61 # define BL31_BASE (ZYNQMP_TRUSTED_SRAM_LIMIT - \ 62 ZYNQMP_BL31_SIZE) 63 # define BL31_PROGBITS_LIMIT (ZYNQMP_TRUSTED_SRAM_LIMIT - 0x6000) 64 # define BL31_LIMIT ZYNQMP_TRUSTED_SRAM_LIMIT 65 #elif ZYNQMP_ATF_LOCATION_ID == ZYNQMP_IN_TRUSTED_DRAM 66 # define BL31_BASE (ZYNQMP_TRUSTED_DRAM_LIMIT - \ 67 ZYNQMP_BL31_SIZE) 68 # define BL31_PROGBITS_LIMIT (ZYNQMP_TRUSTED_DRAM_LIMIT - 0x6000) 69 # define BL31_LIMIT (ZYNQMP_TRUSTED_DRAM_BASE + \ 70 ZYNQMP_TRUSTED_DRAM_SIZE) 71 #else 72 # error "Unsupported ZYNQMP_ATF_LOCATION_ID value" 73 #endif 74 75 /******************************************************************************* 76 * BL32 specific defines. 77 ******************************************************************************/ 78 /* 79 * On ZYNQMP, the TSP can execute either from Trusted SRAM or Trusted DRAM. 80 */ 81 #if ZYNQMP_TSP_RAM_LOCATION_ID == ZYNQMP_IN_TRUSTED_SRAM 82 # define TSP_SEC_MEM_BASE ZYNQMP_TRUSTED_SRAM_BASE 83 # define TSP_SEC_MEM_SIZE ZYNQMP_TRUSTED_SRAM_SIZE 84 # define TSP_PROGBITS_LIMIT (ZYNQMP_TRUSTED_SRAM_LIMIT - \ 85 ZYNQMP_BL31_SIZE) 86 # define BL32_BASE ZYNQMP_TRUSTED_SRAM_BASE 87 # define BL32_LIMIT (ZYNQMP_TRUSTED_SRAM_LIMIT - \ 88 ZYNQMP_BL31_SIZE) 89 #elif ZYNQMP_TSP_RAM_LOCATION_ID == ZYNQMP_IN_TRUSTED_DRAM 90 # define TSP_SEC_MEM_BASE ZYNQMP_TRUSTED_DRAM_BASE 91 # define TSP_SEC_MEM_SIZE (ZYNQMP_TRUSTED_DRAM_LIMIT - \ 92 ZYNQMP_BL31_SIZE) 93 # define BL32_BASE ZYNQMP_TRUSTED_DRAM_BASE 94 # define BL32_LIMIT (ZYNQMP_TRUSTED_DRAM_LIMIT - \ 95 ZYNQMP_BL31_SIZE) 96 #else 97 # error "Unsupported ZYNQMP_TSP_RAM_LOCATION_ID value" 98 #endif 99 100 /* 101 * ID of the secure physical generic timer interrupt used by the TSP. 102 */ 103 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 104 105 /******************************************************************************* 106 * Platform specific page table and MMU setup constants 107 ******************************************************************************/ 108 #define ADDR_SPACE_SIZE (1ull << 32) 109 #define MAX_XLAT_TABLES 5 110 #define MAX_MMAP_REGIONS 7 111 112 #define CACHE_WRITEBACK_SHIFT 6 113 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 114 115 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 116 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 117 /* 118 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 119 * terminology. On a GICv2 system or mode, the lists will be merged and treated 120 * as Group 0 interrupts. 121 */ 122 #define PLAT_ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 123 IRQ_SEC_IPI_APU, \ 124 ARM_IRQ_SEC_SGI_0, \ 125 ARM_IRQ_SEC_SGI_1, \ 126 ARM_IRQ_SEC_SGI_2, \ 127 ARM_IRQ_SEC_SGI_3, \ 128 ARM_IRQ_SEC_SGI_4, \ 129 ARM_IRQ_SEC_SGI_5, \ 130 ARM_IRQ_SEC_SGI_6, \ 131 ARM_IRQ_SEC_SGI_7 132 133 #define PLAT_ARM_G0_IRQS 134 135 #endif /* __PLATFORM_DEF_H__ */ 136