1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include <utils_def.h> 14 #include "../zynqmp_def.h" 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #define PLATFORM_STACK_SIZE 0x440 22 23 #define PLATFORM_CORE_COUNT 4 24 #define PLAT_NUM_POWER_DOMAINS 5 25 #define PLAT_MAX_PWR_LVL U(1) 26 #define PLAT_MAX_RET_STATE U(1) 27 #define PLAT_MAX_OFF_STATE U(2) 28 29 /******************************************************************************* 30 * BL31 specific defines. 31 ******************************************************************************/ 32 /* 33 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 34 * present). BL31_BASE is calculated using the current BL31 debug size plus a 35 * little space for growth. 36 */ 37 #ifndef ZYNQMP_ATF_MEM_BASE 38 #if !DEBUG && defined(SPD_none) 39 # define BL31_BASE 0xfffea000 40 # define BL31_LIMIT 0xffffffff 41 #else 42 # define BL31_BASE 0x1000 43 # define BL31_LIMIT 0x7ffff 44 #endif 45 #else 46 # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 47 # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 48 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 49 # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 50 # endif 51 #endif 52 53 /******************************************************************************* 54 * BL32 specific defines. 55 ******************************************************************************/ 56 #ifndef ZYNQMP_BL32_MEM_BASE 57 # define BL32_BASE 0x60000000 58 # define BL32_LIMIT 0x7fffffff 59 #else 60 # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 61 # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 62 #endif 63 64 /******************************************************************************* 65 * BL33 specific defines. 66 ******************************************************************************/ 67 #ifndef PRELOADED_BL33_BASE 68 # define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 69 #else 70 # define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 71 #endif 72 73 /******************************************************************************* 74 * TSP specific defines. 75 ******************************************************************************/ 76 #define TSP_SEC_MEM_BASE BL32_BASE 77 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 78 79 /* ID of the secure physical generic timer interrupt used by the TSP */ 80 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 81 82 /******************************************************************************* 83 * Platform specific page table and MMU setup constants 84 ******************************************************************************/ 85 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 86 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 87 #define MAX_MMAP_REGIONS 7 88 #define MAX_XLAT_TABLES 5 89 90 #define CACHE_WRITEBACK_SHIFT 6 91 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 92 93 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 94 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 95 /* 96 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 97 * terminology. On a GICv2 system or mode, the lists will be merged and treated 98 * as Group 0 interrupts. 99 */ 100 #if !ZYNQMP_WDT_RESTART 101 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 102 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 103 GIC_INTR_CFG_LEVEL), \ 104 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 105 GIC_INTR_CFG_EDGE), \ 106 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 107 GIC_INTR_CFG_EDGE), \ 108 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 109 GIC_INTR_CFG_EDGE), \ 110 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 111 GIC_INTR_CFG_EDGE), \ 112 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 113 GIC_INTR_CFG_EDGE), \ 114 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 115 GIC_INTR_CFG_EDGE), \ 116 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 117 GIC_INTR_CFG_EDGE), \ 118 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 119 GIC_INTR_CFG_EDGE) 120 #else 121 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 122 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 123 GIC_INTR_CFG_LEVEL), \ 124 INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 125 GIC_INTR_CFG_EDGE), \ 126 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 127 GIC_INTR_CFG_EDGE), \ 128 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 129 GIC_INTR_CFG_EDGE), \ 130 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 131 GIC_INTR_CFG_EDGE), \ 132 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 133 GIC_INTR_CFG_EDGE), \ 134 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 135 GIC_INTR_CFG_EDGE), \ 136 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_EDGE), \ 138 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 139 GIC_INTR_CFG_EDGE), \ 140 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 141 GIC_INTR_CFG_EDGE) 142 #endif 143 144 #define PLAT_ARM_G0_IRQ_PROPS(grp) 145 146 #endif /* PLATFORM_DEF_H */ 147