1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include "../zynqmp_def.h" 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stacks */ 20 #define PLATFORM_STACK_SIZE 0x440 21 22 #define PLATFORM_CORE_COUNT 4 23 #define PLAT_NUM_POWER_DOMAINS 5 24 #define PLAT_MAX_PWR_LVL 1 25 #define PLAT_MAX_RET_STATE 1 26 #define PLAT_MAX_OFF_STATE 2 27 28 /******************************************************************************* 29 * BL31 specific defines. 30 ******************************************************************************/ 31 /* 32 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 33 * present). BL31_BASE is calculated using the current BL31 debug size plus a 34 * little space for growth. 35 */ 36 #ifndef ZYNQMP_ATF_MEM_BASE 37 #if !DEBUG 38 # define BL31_BASE 0xfffea000 39 # define BL31_LIMIT 0xffffffff 40 #else 41 # define BL31_BASE 0x1000 42 # define BL31_LIMIT 0x7ffff 43 #endif 44 #else 45 # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 46 # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 47 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 48 # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 49 # endif 50 #endif 51 52 /******************************************************************************* 53 * BL32 specific defines. 54 ******************************************************************************/ 55 #ifndef ZYNQMP_BL32_MEM_BASE 56 # define BL32_BASE 0x60000000 57 # define BL32_LIMIT 0x7fffffff 58 #else 59 # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 60 # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 61 #endif 62 63 /******************************************************************************* 64 * BL33 specific defines. 65 ******************************************************************************/ 66 #ifndef PRELOADED_BL33_BASE 67 # define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 68 #else 69 # define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 70 #endif 71 72 /******************************************************************************* 73 * TSP specific defines. 74 ******************************************************************************/ 75 #define TSP_SEC_MEM_BASE BL32_BASE 76 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 77 78 /* ID of the secure physical generic timer interrupt used by the TSP */ 79 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 80 81 /******************************************************************************* 82 * Platform specific page table and MMU setup constants 83 ******************************************************************************/ 84 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 85 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 86 #define MAX_MMAP_REGIONS 7 87 #define MAX_XLAT_TABLES 5 88 89 #define CACHE_WRITEBACK_SHIFT 6 90 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 91 92 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 93 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 94 /* 95 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 96 * terminology. On a GICv2 system or mode, the lists will be merged and treated 97 * as Group 0 interrupts. 98 */ 99 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 100 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 101 GIC_INTR_CFG_LEVEL), \ 102 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 103 GIC_INTR_CFG_EDGE), \ 104 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 105 GIC_INTR_CFG_EDGE), \ 106 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 107 GIC_INTR_CFG_EDGE), \ 108 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 109 GIC_INTR_CFG_EDGE), \ 110 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 111 GIC_INTR_CFG_EDGE), \ 112 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 113 GIC_INTR_CFG_EDGE), \ 114 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 115 GIC_INTR_CFG_EDGE), \ 116 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 117 GIC_INTR_CFG_EDGE) 118 119 #define PLAT_ARM_G0_IRQ_PROPS(grp) 120 121 #endif /* __PLATFORM_DEF_H__ */ 122