1c8284409SSoren Brinkmann /* 2c8284409SSoren Brinkmann * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3c8284409SSoren Brinkmann * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5c8284409SSoren Brinkmann */ 6c8284409SSoren Brinkmann 7c8284409SSoren Brinkmann #ifndef __PLATFORM_DEF_H__ 8c8284409SSoren Brinkmann #define __PLATFORM_DEF_H__ 9c8284409SSoren Brinkmann 10c8284409SSoren Brinkmann #include <arch.h> 11c8284409SSoren Brinkmann #include "../zynqmp_def.h" 12c8284409SSoren Brinkmann 13c8284409SSoren Brinkmann /******************************************************************************* 14c8284409SSoren Brinkmann * Generic platform constants 15c8284409SSoren Brinkmann ******************************************************************************/ 16c8284409SSoren Brinkmann 17c8284409SSoren Brinkmann /* Size of cacheable stacks */ 18c8284409SSoren Brinkmann #define PLATFORM_STACK_SIZE 0x440 19c8284409SSoren Brinkmann 20c8284409SSoren Brinkmann #define PLATFORM_CORE_COUNT 4 21c8284409SSoren Brinkmann #define PLAT_NUM_POWER_DOMAINS 5 22c8284409SSoren Brinkmann #define PLAT_MAX_PWR_LVL 1 23c8284409SSoren Brinkmann #define PLAT_MAX_RET_STATE 1 24c8284409SSoren Brinkmann #define PLAT_MAX_OFF_STATE 2 25c8284409SSoren Brinkmann 26c8284409SSoren Brinkmann /******************************************************************************* 27c8284409SSoren Brinkmann * BL31 specific defines. 28c8284409SSoren Brinkmann ******************************************************************************/ 29c8284409SSoren Brinkmann /* 30c8284409SSoren Brinkmann * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 31c8284409SSoren Brinkmann * present). BL31_BASE is calculated using the current BL31 debug size plus a 32c8284409SSoren Brinkmann * little space for growth. 33c8284409SSoren Brinkmann */ 3401555332SSoren Brinkmann #ifndef ZYNQMP_ATF_MEM_BASE 350ab6a242SSoren Brinkmann # define BL31_BASE 0xfffea000 3601555332SSoren Brinkmann # define BL31_LIMIT 0xffffffff 37c8284409SSoren Brinkmann #else 3801555332SSoren Brinkmann # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 3901555332SSoren Brinkmann # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 4001555332SSoren Brinkmann # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 4101555332SSoren Brinkmann # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 4201555332SSoren Brinkmann # endif 43c8284409SSoren Brinkmann #endif 44c8284409SSoren Brinkmann 45c8284409SSoren Brinkmann /******************************************************************************* 46c8284409SSoren Brinkmann * BL32 specific defines. 47c8284409SSoren Brinkmann ******************************************************************************/ 4801555332SSoren Brinkmann #ifndef ZYNQMP_BL32_MEM_BASE 4901555332SSoren Brinkmann # define BL32_BASE 0x60000000 5001555332SSoren Brinkmann # define BL32_LIMIT 0x7fffffff 51c8284409SSoren Brinkmann #else 5201555332SSoren Brinkmann # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 5301555332SSoren Brinkmann # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 54c8284409SSoren Brinkmann #endif 55c8284409SSoren Brinkmann 5601555332SSoren Brinkmann /******************************************************************************* 5701555332SSoren Brinkmann * BL33 specific defines. 5801555332SSoren Brinkmann ******************************************************************************/ 5901555332SSoren Brinkmann #ifndef PRELOADED_BL33_BASE 6001555332SSoren Brinkmann # define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 6101555332SSoren Brinkmann #else 6201555332SSoren Brinkmann # define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 6301555332SSoren Brinkmann #endif 6401555332SSoren Brinkmann 6501555332SSoren Brinkmann /******************************************************************************* 6601555332SSoren Brinkmann * TSP specific defines. 6701555332SSoren Brinkmann ******************************************************************************/ 6801555332SSoren Brinkmann #define TSP_SEC_MEM_BASE BL32_BASE 6901555332SSoren Brinkmann #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 7001555332SSoren Brinkmann 7101555332SSoren Brinkmann /* ID of the secure physical generic timer interrupt used by the TSP */ 72c8284409SSoren Brinkmann #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 73c8284409SSoren Brinkmann 74c8284409SSoren Brinkmann /******************************************************************************* 75c8284409SSoren Brinkmann * Platform specific page table and MMU setup constants 76c8284409SSoren Brinkmann ******************************************************************************/ 777b2a268eSSoren Brinkmann #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 787b2a268eSSoren Brinkmann #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 7947395a23SSoren Brinkmann #define MAX_MMAP_REGIONS 7 80c8284409SSoren Brinkmann #define MAX_XLAT_TABLES 5 81c8284409SSoren Brinkmann 82c8284409SSoren Brinkmann #define CACHE_WRITEBACK_SHIFT 6 83c8284409SSoren Brinkmann #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 84c8284409SSoren Brinkmann 85c8284409SSoren Brinkmann #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 86c8284409SSoren Brinkmann #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 87c8284409SSoren Brinkmann /* 88c8284409SSoren Brinkmann * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 89c8284409SSoren Brinkmann * terminology. On a GICv2 system or mode, the lists will be merged and treated 90c8284409SSoren Brinkmann * as Group 0 interrupts. 91c8284409SSoren Brinkmann */ 92c8284409SSoren Brinkmann #define PLAT_ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 93c8284409SSoren Brinkmann ARM_IRQ_SEC_SGI_0, \ 94c8284409SSoren Brinkmann ARM_IRQ_SEC_SGI_1, \ 95c8284409SSoren Brinkmann ARM_IRQ_SEC_SGI_2, \ 96c8284409SSoren Brinkmann ARM_IRQ_SEC_SGI_3, \ 97c8284409SSoren Brinkmann ARM_IRQ_SEC_SGI_4, \ 98c8284409SSoren Brinkmann ARM_IRQ_SEC_SGI_5, \ 99c8284409SSoren Brinkmann ARM_IRQ_SEC_SGI_6, \ 100c8284409SSoren Brinkmann ARM_IRQ_SEC_SGI_7 101c8284409SSoren Brinkmann 102c8284409SSoren Brinkmann #define PLAT_ARM_G0_IRQS 103c8284409SSoren Brinkmann 104c8284409SSoren Brinkmann #endif /* __PLATFORM_DEF_H__ */ 105