1c8284409SSoren Brinkmann /* 295ad62b2SJeenu Viswambharan * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3c8284409SSoren Brinkmann * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5c8284409SSoren Brinkmann */ 6c8284409SSoren Brinkmann 7c8284409SSoren Brinkmann #ifndef __PLATFORM_DEF_H__ 8c8284409SSoren Brinkmann #define __PLATFORM_DEF_H__ 9c8284409SSoren Brinkmann 10c8284409SSoren Brinkmann #include <arch.h> 1195ad62b2SJeenu Viswambharan #include <gic_common.h> 1295ad62b2SJeenu Viswambharan #include <interrupt_props.h> 13c8284409SSoren Brinkmann #include "../zynqmp_def.h" 14c8284409SSoren Brinkmann 15c8284409SSoren Brinkmann /******************************************************************************* 16c8284409SSoren Brinkmann * Generic platform constants 17c8284409SSoren Brinkmann ******************************************************************************/ 18c8284409SSoren Brinkmann 19c8284409SSoren Brinkmann /* Size of cacheable stacks */ 20c8284409SSoren Brinkmann #define PLATFORM_STACK_SIZE 0x440 21c8284409SSoren Brinkmann 22c8284409SSoren Brinkmann #define PLATFORM_CORE_COUNT 4 23c8284409SSoren Brinkmann #define PLAT_NUM_POWER_DOMAINS 5 24c8284409SSoren Brinkmann #define PLAT_MAX_PWR_LVL 1 25c8284409SSoren Brinkmann #define PLAT_MAX_RET_STATE 1 26c8284409SSoren Brinkmann #define PLAT_MAX_OFF_STATE 2 27c8284409SSoren Brinkmann 28c8284409SSoren Brinkmann /******************************************************************************* 29c8284409SSoren Brinkmann * BL31 specific defines. 30c8284409SSoren Brinkmann ******************************************************************************/ 31c8284409SSoren Brinkmann /* 32c8284409SSoren Brinkmann * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 33c8284409SSoren Brinkmann * present). BL31_BASE is calculated using the current BL31 debug size plus a 34c8284409SSoren Brinkmann * little space for growth. 35c8284409SSoren Brinkmann */ 3601555332SSoren Brinkmann #ifndef ZYNQMP_ATF_MEM_BASE 370ab6a242SSoren Brinkmann # define BL31_BASE 0xfffea000 3801555332SSoren Brinkmann # define BL31_LIMIT 0xffffffff 39c8284409SSoren Brinkmann #else 4001555332SSoren Brinkmann # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 4101555332SSoren Brinkmann # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 4201555332SSoren Brinkmann # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 4301555332SSoren Brinkmann # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 4401555332SSoren Brinkmann # endif 45c8284409SSoren Brinkmann #endif 46c8284409SSoren Brinkmann 47c8284409SSoren Brinkmann /******************************************************************************* 48c8284409SSoren Brinkmann * BL32 specific defines. 49c8284409SSoren Brinkmann ******************************************************************************/ 5001555332SSoren Brinkmann #ifndef ZYNQMP_BL32_MEM_BASE 5101555332SSoren Brinkmann # define BL32_BASE 0x60000000 5201555332SSoren Brinkmann # define BL32_LIMIT 0x7fffffff 53c8284409SSoren Brinkmann #else 5401555332SSoren Brinkmann # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 5501555332SSoren Brinkmann # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 56c8284409SSoren Brinkmann #endif 57c8284409SSoren Brinkmann 5801555332SSoren Brinkmann /******************************************************************************* 5901555332SSoren Brinkmann * BL33 specific defines. 6001555332SSoren Brinkmann ******************************************************************************/ 6101555332SSoren Brinkmann #ifndef PRELOADED_BL33_BASE 6201555332SSoren Brinkmann # define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 6301555332SSoren Brinkmann #else 6401555332SSoren Brinkmann # define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 6501555332SSoren Brinkmann #endif 6601555332SSoren Brinkmann 6701555332SSoren Brinkmann /******************************************************************************* 6801555332SSoren Brinkmann * TSP specific defines. 6901555332SSoren Brinkmann ******************************************************************************/ 7001555332SSoren Brinkmann #define TSP_SEC_MEM_BASE BL32_BASE 7101555332SSoren Brinkmann #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 7201555332SSoren Brinkmann 7301555332SSoren Brinkmann /* ID of the secure physical generic timer interrupt used by the TSP */ 74c8284409SSoren Brinkmann #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 75c8284409SSoren Brinkmann 76c8284409SSoren Brinkmann /******************************************************************************* 77c8284409SSoren Brinkmann * Platform specific page table and MMU setup constants 78c8284409SSoren Brinkmann ******************************************************************************/ 79*5724481fSDavid Cunado #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 80*5724481fSDavid Cunado #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 8147395a23SSoren Brinkmann #define MAX_MMAP_REGIONS 7 82c8284409SSoren Brinkmann #define MAX_XLAT_TABLES 5 83c8284409SSoren Brinkmann 84c8284409SSoren Brinkmann #define CACHE_WRITEBACK_SHIFT 6 85c8284409SSoren Brinkmann #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 86c8284409SSoren Brinkmann 87c8284409SSoren Brinkmann #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 88c8284409SSoren Brinkmann #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 89c8284409SSoren Brinkmann /* 9095ad62b2SJeenu Viswambharan * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 91c8284409SSoren Brinkmann * terminology. On a GICv2 system or mode, the lists will be merged and treated 92c8284409SSoren Brinkmann * as Group 0 interrupts. 93c8284409SSoren Brinkmann */ 9495ad62b2SJeenu Viswambharan #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 9595ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 9695ad62b2SJeenu Viswambharan GIC_INTR_CFG_LEVEL), \ 9795ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 9895ad62b2SJeenu Viswambharan GIC_INTR_CFG_EDGE), \ 9995ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 10095ad62b2SJeenu Viswambharan GIC_INTR_CFG_EDGE), \ 10195ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 10295ad62b2SJeenu Viswambharan GIC_INTR_CFG_EDGE), \ 10395ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 10495ad62b2SJeenu Viswambharan GIC_INTR_CFG_EDGE), \ 10595ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 10695ad62b2SJeenu Viswambharan GIC_INTR_CFG_EDGE), \ 10795ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 10895ad62b2SJeenu Viswambharan GIC_INTR_CFG_EDGE), \ 10995ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 11095ad62b2SJeenu Viswambharan GIC_INTR_CFG_EDGE), \ 11195ad62b2SJeenu Viswambharan INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 11295ad62b2SJeenu Viswambharan GIC_INTR_CFG_EDGE) 113c8284409SSoren Brinkmann 11495ad62b2SJeenu Viswambharan #define PLAT_ARM_G0_IRQ_PROPS(grp) 115c8284409SSoren Brinkmann 116c8284409SSoren Brinkmann #endif /* __PLATFORM_DEF_H__ */ 117