1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 #include <string.h> 9 10 #include <common/debug.h> 11 #include <drivers/generic_delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables.h> 14 #include <plat_ipi.h> 15 #include <plat_private.h> 16 #include <plat/common/platform.h> 17 18 #include "pm_api_sys.h" 19 20 /* 21 * Table of regions to map using the MMU. 22 * This doesn't include TZRAM as the 'mem_layout' argument passed to 23 * configure_mmu_elx() will give the available subset of that, 24 */ 25 const mmap_region_t plat_arm_mmap[] = { 26 { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 27 { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 28 { CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 29 {0} 30 }; 31 32 static unsigned int zynqmp_get_silicon_ver(void) 33 { 34 static unsigned int ver; 35 36 if (!ver) { 37 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + 38 ZYNQMP_CSU_VERSION_OFFSET); 39 ver &= ZYNQMP_SILICON_VER_MASK; 40 ver >>= ZYNQMP_SILICON_VER_SHIFT; 41 } 42 43 return ver; 44 } 45 46 unsigned int zynqmp_get_uart_clk(void) 47 { 48 unsigned int ver = zynqmp_get_silicon_ver(); 49 50 if (ver == ZYNQMP_CSU_VERSION_QEMU) 51 return 133000000; 52 else 53 return 100000000; 54 } 55 56 #if LOG_LEVEL >= LOG_LEVEL_NOTICE 57 static const struct { 58 unsigned int id; 59 unsigned int ver; 60 char *name; 61 bool evexists; 62 } zynqmp_devices[] = { 63 { 64 .id = 0x10, 65 .name = "XCZU3EG", 66 }, 67 { 68 .id = 0x10, 69 .ver = 0x2c, 70 .name = "XCZU3CG", 71 }, 72 { 73 .id = 0x11, 74 .name = "XCZU2EG", 75 }, 76 { 77 .id = 0x11, 78 .ver = 0x2c, 79 .name = "XCZU2CG", 80 }, 81 { 82 .id = 0x20, 83 .name = "XCZU5EV", 84 .evexists = true, 85 }, 86 { 87 .id = 0x20, 88 .ver = 0x100, 89 .name = "XCZU5EG", 90 .evexists = true, 91 }, 92 { 93 .id = 0x20, 94 .ver = 0x12c, 95 .name = "XCZU5CG", 96 }, 97 { 98 .id = 0x21, 99 .name = "XCZU4EV", 100 .evexists = true, 101 }, 102 { 103 .id = 0x21, 104 .ver = 0x100, 105 .name = "XCZU4EG", 106 .evexists = true, 107 }, 108 { 109 .id = 0x21, 110 .ver = 0x12c, 111 .name = "XCZU4CG", 112 }, 113 { 114 .id = 0x30, 115 .name = "XCZU7EV", 116 .evexists = true, 117 }, 118 { 119 .id = 0x30, 120 .ver = 0x100, 121 .name = "XCZU7EG", 122 .evexists = true, 123 }, 124 { 125 .id = 0x30, 126 .ver = 0x12c, 127 .name = "XCZU7CG", 128 }, 129 { 130 .id = 0x38, 131 .name = "XCZU9EG", 132 }, 133 { 134 .id = 0x38, 135 .ver = 0x2c, 136 .name = "XCZU9CG", 137 }, 138 { 139 .id = 0x39, 140 .name = "XCZU6EG", 141 }, 142 { 143 .id = 0x39, 144 .ver = 0x2c, 145 .name = "XCZU6CG", 146 }, 147 { 148 .id = 0x40, 149 .name = "XCZU11EG", 150 }, 151 { /* For testing purpose only */ 152 .id = 0x50, 153 .ver = 0x2c, 154 .name = "XCZU15CG", 155 }, 156 { 157 .id = 0x50, 158 .name = "XCZU15EG", 159 }, 160 { 161 .id = 0x58, 162 .name = "XCZU19EG", 163 }, 164 { 165 .id = 0x59, 166 .name = "XCZU17EG", 167 }, 168 { 169 .id = 0x60, 170 .name = "XCZU28DR", 171 }, 172 { 173 .id = 0x61, 174 .name = "XCZU21DR", 175 }, 176 { 177 .id = 0x62, 178 .name = "XCZU29DR", 179 }, 180 { 181 .id = 0x63, 182 .name = "XCZU23DR", 183 }, 184 { 185 .id = 0x64, 186 .name = "XCZU27DR", 187 }, 188 { 189 .id = 0x65, 190 .name = "XCZU25DR", 191 }, 192 { 193 .id = 0x66, 194 .name = "XCZU39DR", 195 }, 196 { 197 .id = 0x7d, 198 .name = "XCZU43DR", 199 }, 200 { 201 .id = 0x78, 202 .name = "XCZU46DR", 203 }, 204 { 205 .id = 0x7f, 206 .name = "XCZU47DR", 207 }, 208 { 209 .id = 0x7b, 210 .name = "XCZU48DR", 211 }, 212 { 213 .id = 0x7e, 214 .name = "XCZU49DR", 215 }, 216 }; 217 218 #define ZYNQMP_PL_STATUS_BIT 9 219 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT) 220 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK) 221 222 #define SILICON_ID_XCK26 0x4724093 223 224 static char *zynqmp_get_silicon_idcode_name(void) 225 { 226 uint32_t id, ver, chipid[2]; 227 size_t i, j, len; 228 const char *name = "EG/EV"; 229 230 #ifdef IMAGE_BL32 231 /* 232 * For BL32, get the chip id info directly by reading corresponding 233 * registers instead of making pm call. This has limitation 234 * that these registers should be configured to have access 235 * from APU which is default case. 236 */ 237 chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); 238 chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET); 239 #else 240 if (pm_get_chipid(chipid) != PM_RET_SUCCESS) 241 return "XCZUUNKN"; 242 #endif 243 244 id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | 245 ZYNQMP_CSU_IDCODE_SVD_MASK); 246 id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; 247 ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT; 248 249 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { 250 if (zynqmp_devices[i].id == id && 251 zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) 252 break; 253 } 254 255 if (i >= ARRAY_SIZE(zynqmp_devices)) { 256 if (chipid[0] == SILICON_ID_XCK26) { 257 return "XCK26"; 258 } else { 259 return "XCZUUNKN"; 260 } 261 } 262 263 if (!zynqmp_devices[i].evexists) 264 return zynqmp_devices[i].name; 265 266 if (ver & ZYNQMP_PL_STATUS_MASK) 267 return zynqmp_devices[i].name; 268 269 len = strlen(zynqmp_devices[i].name) - 2; 270 for (j = 0; j < strlen(name); j++) { 271 zynqmp_devices[i].name[len] = name[j]; 272 len++; 273 } 274 zynqmp_devices[i].name[len] = '\0'; 275 276 return zynqmp_devices[i].name; 277 } 278 279 static unsigned int zynqmp_get_rtl_ver(void) 280 { 281 uint32_t ver; 282 283 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); 284 ver &= ZYNQMP_RTL_VER_MASK; 285 ver >>= ZYNQMP_RTL_VER_SHIFT; 286 287 return ver; 288 } 289 290 static char *zynqmp_print_silicon_idcode(void) 291 { 292 uint32_t id, maskid, tmp; 293 294 id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); 295 296 tmp = id; 297 tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK | 298 ZYNQMP_CSU_IDCODE_FAMILY_MASK; 299 maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT | 300 ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT; 301 if (tmp != maskid) { 302 ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid); 303 return "UNKN"; 304 } 305 VERBOSE("Xilinx IDCODE 0x%x\n", id); 306 return zynqmp_get_silicon_idcode_name(); 307 } 308 309 static unsigned int zynqmp_get_ps_ver(void) 310 { 311 uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); 312 313 ver &= ZYNQMP_PS_VER_MASK; 314 ver >>= ZYNQMP_PS_VER_SHIFT; 315 316 return ver + 1; 317 } 318 319 static void zynqmp_print_platform_name(void) 320 { 321 unsigned int ver = zynqmp_get_silicon_ver(); 322 unsigned int rtl = zynqmp_get_rtl_ver(); 323 char *label = "Unknown"; 324 325 switch (ver) { 326 case ZYNQMP_CSU_VERSION_QEMU: 327 label = "QEMU"; 328 break; 329 case ZYNQMP_CSU_VERSION_SILICON: 330 label = "silicon"; 331 break; 332 default: 333 /* Do nothing in default case */ 334 break; 335 } 336 337 NOTICE("TF-A running on %s/%s v%d/RTL%d.%d at 0x%x\n", 338 zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(), 339 (rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE); 340 } 341 #else 342 static inline void zynqmp_print_platform_name(void) { } 343 #endif 344 345 unsigned int zynqmp_get_bootmode(void) 346 { 347 uint32_t r; 348 unsigned int ret; 349 350 ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r); 351 352 if (ret != PM_RET_SUCCESS) 353 r = mmio_read_32(CRL_APB_BOOT_MODE_USER); 354 355 return r & CRL_APB_BOOT_MODE_MASK; 356 } 357 358 void zynqmp_config_setup(void) 359 { 360 uint64_t counter_freq; 361 362 /* Configure IPI data for ZynqMP */ 363 zynqmp_ipi_config_table_init(); 364 365 zynqmp_print_platform_name(); 366 367 /* Configure counter frequency */ 368 counter_freq = read_cntfrq_el0(); 369 if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) { 370 write_cntfrq_el0(plat_get_syscnt_freq2()); 371 } 372 373 generic_delay_timer_init(); 374 } 375 376 unsigned int plat_get_syscnt_freq2(void) 377 { 378 unsigned int ver = zynqmp_get_silicon_ver(); 379 380 if (ver == ZYNQMP_CSU_VERSION_QEMU) 381 return 65000000; 382 else 383 return mmio_read_32(IOU_SCNTRS_BASEFREQ); 384 } 385