1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 #include <string.h> 9 10 #include <common/debug.h> 11 #include <drivers/generic_delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables.h> 14 #include <plat_ipi.h> 15 #include <plat_private.h> 16 #include <plat/common/platform.h> 17 18 #include "pm_api_sys.h" 19 20 /* 21 * Table of regions to map using the MMU. 22 * This doesn't include TZRAM as the 'mem_layout' argument passed to 23 * configure_mmu_elx() will give the available subset of that, 24 */ 25 const mmap_region_t plat_arm_mmap[] = { 26 { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 27 { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 28 { CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 29 {0} 30 }; 31 32 static unsigned int zynqmp_get_silicon_ver(void) 33 { 34 static unsigned int ver; 35 36 if (!ver) { 37 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + 38 ZYNQMP_CSU_VERSION_OFFSET); 39 ver &= ZYNQMP_SILICON_VER_MASK; 40 ver >>= ZYNQMP_SILICON_VER_SHIFT; 41 } 42 43 return ver; 44 } 45 46 unsigned int zynqmp_get_uart_clk(void) 47 { 48 unsigned int ver = zynqmp_get_silicon_ver(); 49 50 if (ver == ZYNQMP_CSU_VERSION_QEMU) 51 return 133000000; 52 else 53 return 100000000; 54 } 55 56 #if LOG_LEVEL >= LOG_LEVEL_NOTICE 57 static const struct { 58 unsigned int id; 59 unsigned int ver; 60 char *name; 61 bool evexists; 62 } zynqmp_devices[] = { 63 { 64 .id = 0x10, 65 .name = "3EG", 66 }, 67 { 68 .id = 0x10, 69 .ver = 0x2c, 70 .name = "3CG", 71 }, 72 { 73 .id = 0x11, 74 .name = "2EG", 75 }, 76 { 77 .id = 0x11, 78 .ver = 0x2c, 79 .name = "2CG", 80 }, 81 { 82 .id = 0x20, 83 .name = "5EV", 84 .evexists = true, 85 }, 86 { 87 .id = 0x20, 88 .ver = 0x100, 89 .name = "5EG", 90 .evexists = true, 91 }, 92 { 93 .id = 0x20, 94 .ver = 0x12c, 95 .name = "5CG", 96 }, 97 { 98 .id = 0x21, 99 .name = "4EV", 100 .evexists = true, 101 }, 102 { 103 .id = 0x21, 104 .ver = 0x100, 105 .name = "4EG", 106 .evexists = true, 107 }, 108 { 109 .id = 0x21, 110 .ver = 0x12c, 111 .name = "4CG", 112 }, 113 { 114 .id = 0x30, 115 .name = "7EV", 116 .evexists = true, 117 }, 118 { 119 .id = 0x30, 120 .ver = 0x100, 121 .name = "7EG", 122 .evexists = true, 123 }, 124 { 125 .id = 0x30, 126 .ver = 0x12c, 127 .name = "7CG", 128 }, 129 { 130 .id = 0x38, 131 .name = "9EG", 132 }, 133 { 134 .id = 0x38, 135 .ver = 0x2c, 136 .name = "9CG", 137 }, 138 { 139 .id = 0x39, 140 .name = "6EG", 141 }, 142 { 143 .id = 0x39, 144 .ver = 0x2c, 145 .name = "6CG", 146 }, 147 { 148 .id = 0x40, 149 .name = "11EG", 150 }, 151 { /* For testing purpose only */ 152 .id = 0x50, 153 .ver = 0x2c, 154 .name = "15CG", 155 }, 156 { 157 .id = 0x50, 158 .name = "15EG", 159 }, 160 { 161 .id = 0x58, 162 .name = "19EG", 163 }, 164 { 165 .id = 0x59, 166 .name = "17EG", 167 }, 168 { 169 .id = 0x60, 170 .name = "28DR", 171 }, 172 { 173 .id = 0x61, 174 .name = "21DR", 175 }, 176 { 177 .id = 0x62, 178 .name = "29DR", 179 }, 180 { 181 .id = 0x63, 182 .name = "23DR", 183 }, 184 { 185 .id = 0x64, 186 .name = "27DR", 187 }, 188 { 189 .id = 0x65, 190 .name = "25DR", 191 }, 192 { 193 .id = 0x66, 194 .name = "39DR", 195 }, 196 { 197 .id = 0x7d, 198 .name = "43DR", 199 }, 200 { 201 .id = 0x78, 202 .name = "46DR", 203 }, 204 { 205 .id = 0x7f, 206 .name = "47DR", 207 }, 208 { 209 .id = 0x7b, 210 .name = "48DR", 211 }, 212 { 213 .id = 0x7e, 214 .name = "49DR", 215 }, 216 }; 217 218 #define ZYNQMP_PL_STATUS_BIT 9 219 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT) 220 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK) 221 222 static char *zynqmp_get_silicon_idcode_name(void) 223 { 224 uint32_t id, ver, chipid[2]; 225 size_t i, j, len; 226 const char *name = "EG/EV"; 227 228 #ifdef IMAGE_BL32 229 /* 230 * For BL32, get the chip id info directly by reading corresponding 231 * registers instead of making pm call. This has limitation 232 * that these registers should be configured to have access 233 * from APU which is default case. 234 */ 235 chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); 236 chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET); 237 #else 238 if (pm_get_chipid(chipid) != PM_RET_SUCCESS) 239 return "UNKN"; 240 #endif 241 242 id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | 243 ZYNQMP_CSU_IDCODE_SVD_MASK); 244 id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; 245 ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT; 246 247 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { 248 if (zynqmp_devices[i].id == id && 249 zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) 250 break; 251 } 252 253 if (i >= ARRAY_SIZE(zynqmp_devices)) 254 return "UNKN"; 255 256 if (!zynqmp_devices[i].evexists) 257 return zynqmp_devices[i].name; 258 259 if (ver & ZYNQMP_PL_STATUS_MASK) 260 return zynqmp_devices[i].name; 261 262 len = strlen(zynqmp_devices[i].name) - 2; 263 for (j = 0; j < strlen(name); j++) { 264 zynqmp_devices[i].name[len] = name[j]; 265 len++; 266 } 267 zynqmp_devices[i].name[len] = '\0'; 268 269 return zynqmp_devices[i].name; 270 } 271 272 static unsigned int zynqmp_get_rtl_ver(void) 273 { 274 uint32_t ver; 275 276 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); 277 ver &= ZYNQMP_RTL_VER_MASK; 278 ver >>= ZYNQMP_RTL_VER_SHIFT; 279 280 return ver; 281 } 282 283 static char *zynqmp_print_silicon_idcode(void) 284 { 285 uint32_t id, maskid, tmp; 286 287 id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); 288 289 tmp = id; 290 tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK | 291 ZYNQMP_CSU_IDCODE_FAMILY_MASK; 292 maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT | 293 ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT; 294 if (tmp != maskid) { 295 ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid); 296 return "UNKN"; 297 } 298 VERBOSE("Xilinx IDCODE 0x%x\n", id); 299 return zynqmp_get_silicon_idcode_name(); 300 } 301 302 static unsigned int zynqmp_get_ps_ver(void) 303 { 304 uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); 305 306 ver &= ZYNQMP_PS_VER_MASK; 307 ver >>= ZYNQMP_PS_VER_SHIFT; 308 309 return ver + 1; 310 } 311 312 static void zynqmp_print_platform_name(void) 313 { 314 unsigned int ver = zynqmp_get_silicon_ver(); 315 unsigned int rtl = zynqmp_get_rtl_ver(); 316 char *label = "Unknown"; 317 318 switch (ver) { 319 case ZYNQMP_CSU_VERSION_QEMU: 320 label = "QEMU"; 321 break; 322 case ZYNQMP_CSU_VERSION_SILICON: 323 label = "silicon"; 324 break; 325 default: 326 /* Do nothing in default case */ 327 break; 328 } 329 330 NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x\n", 331 zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(), 332 (rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE); 333 } 334 #else 335 static inline void zynqmp_print_platform_name(void) { } 336 #endif 337 338 unsigned int zynqmp_get_bootmode(void) 339 { 340 uint32_t r; 341 unsigned int ret; 342 343 ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r); 344 345 if (ret != PM_RET_SUCCESS) 346 r = mmio_read_32(CRL_APB_BOOT_MODE_USER); 347 348 return r & CRL_APB_BOOT_MODE_MASK; 349 } 350 351 void zynqmp_config_setup(void) 352 { 353 uint64_t counter_freq; 354 355 /* Configure IPI data for ZynqMP */ 356 zynqmp_ipi_config_table_init(); 357 358 zynqmp_print_platform_name(); 359 360 /* Configure counter frequency */ 361 counter_freq = read_cntfrq_el0(); 362 if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) { 363 write_cntfrq_el0(plat_get_syscnt_freq2()); 364 } 365 366 generic_delay_timer_init(); 367 } 368 369 unsigned int plat_get_syscnt_freq2(void) 370 { 371 unsigned int ver = zynqmp_get_silicon_ver(); 372 373 if (ver == ZYNQMP_CSU_VERSION_QEMU) 374 return 65000000; 375 else 376 return mmio_read_32(IOU_SCNTRS_BASEFREQ); 377 } 378