1 /* 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 #include <string.h> 9 10 #include <common/debug.h> 11 #include <drivers/generic_delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables.h> 14 #include <plat_ipi.h> 15 #include <plat_private.h> 16 #include <plat/common/platform.h> 17 18 #include "pm_api_sys.h" 19 20 /* 21 * Table of regions to map using the MMU. 22 * This doesn't include TZRAM as the 'mem_layout' argument passed to 23 * configure_mmu_elx() will give the available subset of that, 24 */ 25 const mmap_region_t plat_arm_mmap[] = { 26 { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 27 { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 28 { CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, 29 {0} 30 }; 31 32 static unsigned int zynqmp_get_silicon_ver(void) 33 { 34 static unsigned int ver; 35 36 if (!ver) { 37 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + 38 ZYNQMP_CSU_VERSION_OFFSET); 39 ver &= ZYNQMP_SILICON_VER_MASK; 40 ver >>= ZYNQMP_SILICON_VER_SHIFT; 41 } 42 43 return ver; 44 } 45 46 unsigned int zynqmp_get_uart_clk(void) 47 { 48 unsigned int ver = zynqmp_get_silicon_ver(); 49 50 if (ver == ZYNQMP_CSU_VERSION_QEMU) { 51 return 133000000; 52 } else { 53 return 100000000; 54 } 55 } 56 57 #if LOG_LEVEL >= LOG_LEVEL_NOTICE 58 static const struct { 59 unsigned int id; 60 unsigned int ver; 61 char *name; 62 bool evexists; 63 } zynqmp_devices[] = { 64 { 65 .id = 0x10, 66 .name = "XCZU3EG", 67 }, 68 { 69 .id = 0x10, 70 .ver = 0x2c, 71 .name = "XCZU3CG", 72 }, 73 { 74 .id = 0x11, 75 .name = "XCZU2EG", 76 }, 77 { 78 .id = 0x11, 79 .ver = 0x2c, 80 .name = "XCZU2CG", 81 }, 82 { 83 .id = 0x20, 84 .name = "XCZU5EV", 85 .evexists = true, 86 }, 87 { 88 .id = 0x20, 89 .ver = 0x100, 90 .name = "XCZU5EG", 91 .evexists = true, 92 }, 93 { 94 .id = 0x20, 95 .ver = 0x12c, 96 .name = "XCZU5CG", 97 }, 98 { 99 .id = 0x21, 100 .name = "XCZU4EV", 101 .evexists = true, 102 }, 103 { 104 .id = 0x21, 105 .ver = 0x100, 106 .name = "XCZU4EG", 107 .evexists = true, 108 }, 109 { 110 .id = 0x21, 111 .ver = 0x12c, 112 .name = "XCZU4CG", 113 }, 114 { 115 .id = 0x30, 116 .name = "XCZU7EV", 117 .evexists = true, 118 }, 119 { 120 .id = 0x30, 121 .ver = 0x100, 122 .name = "XCZU7EG", 123 .evexists = true, 124 }, 125 { 126 .id = 0x30, 127 .ver = 0x12c, 128 .name = "XCZU7CG", 129 }, 130 { 131 .id = 0x38, 132 .name = "XCZU9EG", 133 }, 134 { 135 .id = 0x38, 136 .ver = 0x2c, 137 .name = "XCZU9CG", 138 }, 139 { 140 .id = 0x39, 141 .name = "XCZU6EG", 142 }, 143 { 144 .id = 0x39, 145 .ver = 0x2c, 146 .name = "XCZU6CG", 147 }, 148 { 149 .id = 0x40, 150 .name = "XCZU11EG", 151 }, 152 { 153 .id = 0x50, 154 .name = "XCZU15EG", 155 }, 156 { 157 .id = 0x58, 158 .name = "XCZU19EG", 159 }, 160 { 161 .id = 0x59, 162 .name = "XCZU17EG", 163 }, 164 { 165 .id = 0x60, 166 .name = "XCZU28DR", 167 }, 168 { 169 .id = 0x61, 170 .name = "XCZU21DR", 171 }, 172 { 173 .id = 0x62, 174 .name = "XCZU29DR", 175 }, 176 { 177 .id = 0x63, 178 .name = "XCZU23DR", 179 }, 180 { 181 .id = 0x64, 182 .name = "XCZU27DR", 183 }, 184 { 185 .id = 0x65, 186 .name = "XCZU25DR", 187 }, 188 { 189 .id = 0x66, 190 .name = "XCZU39DR", 191 }, 192 { 193 .id = 0x7d, 194 .name = "XCZU43DR", 195 }, 196 { 197 .id = 0x78, 198 .name = "XCZU46DR", 199 }, 200 { 201 .id = 0x7f, 202 .name = "XCZU47DR", 203 }, 204 { 205 .id = 0x7b, 206 .name = "XCZU48DR", 207 }, 208 { 209 .id = 0x7e, 210 .name = "XCZU49DR", 211 }, 212 }; 213 214 #define ZYNQMP_PL_STATUS_BIT 9 215 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT) 216 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK) 217 218 #define SILICON_ID_XCK26 0x4724093 219 220 static char *zynqmp_get_silicon_idcode_name(void) 221 { 222 uint32_t id, ver, chipid[2]; 223 size_t i, j, len; 224 const char *name = "EG/EV"; 225 226 #ifdef IMAGE_BL32 227 /* 228 * For BL32, get the chip id info directly by reading corresponding 229 * registers instead of making pm call. This has limitation 230 * that these registers should be configured to have access 231 * from APU which is default case. 232 */ 233 chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); 234 chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET); 235 #else 236 if (pm_get_chipid(chipid) != PM_RET_SUCCESS) { 237 return "XCZUUNKN"; 238 } 239 #endif 240 241 id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | 242 ZYNQMP_CSU_IDCODE_SVD_MASK); 243 id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; 244 ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT; 245 246 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { 247 if (zynqmp_devices[i].id == id && 248 zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK)) { 249 break; 250 } 251 } 252 253 if (i >= ARRAY_SIZE(zynqmp_devices)) { 254 if (chipid[0] == SILICON_ID_XCK26) { 255 return "XCK26"; 256 } else { 257 return "XCZUUNKN"; 258 } 259 } 260 261 if (!zynqmp_devices[i].evexists) { 262 return zynqmp_devices[i].name; 263 } 264 265 if ((ver & ZYNQMP_PL_STATUS_MASK) != 0U) { 266 return zynqmp_devices[i].name; 267 } 268 269 len = strlen(zynqmp_devices[i].name) - 2; 270 for (j = 0; j < strlen(name); j++) { 271 zynqmp_devices[i].name[len] = name[j]; 272 len++; 273 } 274 zynqmp_devices[i].name[len] = '\0'; 275 276 return zynqmp_devices[i].name; 277 } 278 279 static unsigned int zynqmp_get_rtl_ver(void) 280 { 281 uint32_t ver; 282 283 ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); 284 ver &= ZYNQMP_RTL_VER_MASK; 285 ver >>= ZYNQMP_RTL_VER_SHIFT; 286 287 return ver; 288 } 289 290 static char *zynqmp_print_silicon_idcode(void) 291 { 292 uint32_t id, maskid, tmp; 293 294 id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); 295 296 tmp = id; 297 tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK | 298 ZYNQMP_CSU_IDCODE_FAMILY_MASK; 299 maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT | 300 ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT; 301 if (tmp != maskid) { 302 ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid); 303 return "UNKN"; 304 } 305 VERBOSE("Xilinx IDCODE 0x%x\n", id); 306 return zynqmp_get_silicon_idcode_name(); 307 } 308 309 static unsigned int zynqmp_get_ps_ver(void) 310 { 311 uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); 312 313 ver &= ZYNQMP_PS_VER_MASK; 314 ver >>= ZYNQMP_PS_VER_SHIFT; 315 316 return ver + 1; 317 } 318 319 static void zynqmp_print_platform_name(void) 320 { 321 unsigned int ver = zynqmp_get_silicon_ver(); 322 unsigned int rtl = zynqmp_get_rtl_ver(); 323 char *label = "Unknown"; 324 325 switch (ver) { 326 case ZYNQMP_CSU_VERSION_QEMU: 327 label = "QEMU"; 328 break; 329 case ZYNQMP_CSU_VERSION_SILICON: 330 label = "silicon"; 331 break; 332 default: 333 /* Do nothing in default case */ 334 break; 335 } 336 337 VERBOSE("TF-A running on %s/%s at 0x%x\n", 338 zynqmp_print_silicon_idcode(), label, BL31_BASE); 339 VERBOSE("TF-A running on v%d/RTL%d.%d\n", 340 zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf); 341 } 342 #else 343 static inline void zynqmp_print_platform_name(void) { } 344 #endif 345 346 unsigned int zynqmp_get_bootmode(void) 347 { 348 uint32_t r; 349 unsigned int ret; 350 351 ret = pm_mmio_read(CRL_APB_BOOT_MODE_USER, &r); 352 353 if (ret != PM_RET_SUCCESS) { 354 r = mmio_read_32(CRL_APB_BOOT_MODE_USER); 355 } 356 357 return r & CRL_APB_BOOT_MODE_MASK; 358 } 359 360 void zynqmp_config_setup(void) 361 { 362 uint64_t counter_freq; 363 364 /* Configure IPI data for ZynqMP */ 365 zynqmp_ipi_config_table_init(); 366 367 zynqmp_print_platform_name(); 368 369 /* Configure counter frequency */ 370 counter_freq = read_cntfrq_el0(); 371 if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) { 372 write_cntfrq_el0(plat_get_syscnt_freq2()); 373 } 374 375 generic_delay_timer_init(); 376 } 377 378 unsigned int plat_get_syscnt_freq2(void) 379 { 380 unsigned int ver = zynqmp_get_silicon_ver(); 381 382 if (ver == ZYNQMP_CSU_VERSION_QEMU) { 383 return 65000000; 384 } else { 385 return mmio_read_32(IOU_SCNTRS_BASEFREQ); 386 } 387 } 388