1*1d333e69SMichal Simek /* 2*1d333e69SMichal Simek * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*1d333e69SMichal Simek * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4*1d333e69SMichal Simek * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 5*1d333e69SMichal Simek * 6*1d333e69SMichal Simek * SPDX-License-Identifier: BSD-3-Clause 7*1d333e69SMichal Simek */ 8*1d333e69SMichal Simek 9*1d333e69SMichal Simek #ifndef PLAT_PRIVATE_H 10*1d333e69SMichal Simek #define PLAT_PRIVATE_H 11*1d333e69SMichal Simek 12*1d333e69SMichal Simek #include <lib/xlat_tables/xlat_tables_v2.h> 13*1d333e69SMichal Simek 14*1d333e69SMichal Simek void versal_net_config_setup(void); 15*1d333e69SMichal Simek 16*1d333e69SMichal Simek const mmap_region_t *plat_versal_net_get_mmap(void); 17*1d333e69SMichal Simek 18*1d333e69SMichal Simek void plat_versal_net_gic_driver_init(void); 19*1d333e69SMichal Simek void plat_versal_net_gic_init(void); 20*1d333e69SMichal Simek void plat_versal_net_gic_cpuif_enable(void); 21*1d333e69SMichal Simek void plat_versal_net_gic_pcpu_init(void); 22*1d333e69SMichal Simek 23*1d333e69SMichal Simek extern uint32_t cpu_clock, platform_id, platform_version; 24*1d333e69SMichal Simek void board_detection(void); 25*1d333e69SMichal Simek char *board_name_decode(void); 26*1d333e69SMichal Simek uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 27*1d333e69SMichal Simek uint64_t x4, void *cookie, void *handle, uint64_t flags); 28*1d333e69SMichal Simek int32_t sip_svc_setup_init(void); 29*1d333e69SMichal Simek 30*1d333e69SMichal Simek #define PM_GET_CHIPID (24U) 31*1d333e69SMichal Simek #define IOCTL_OSPI_MUX_SELECT (21U) 32*1d333e69SMichal Simek 33*1d333e69SMichal Simek #endif /* PLAT_PRIVATE_H */ 34