Merge "fix(versal-net): add fallback on handoff failure" into integration

fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To

fix(versal-net): add fallback on handoff failure

On the Versal-Net platform, booting can fail during ELF loading due to
the absence of a PLM handoff, preventing the system from booting
further.

To address this, a fallback mechanism has been introduced that allows
the boot process to continue even if the PLM handoff is not provided
only in debug builds with jtag boot mode.

Change-Id: Ib8d92ab8400b7a63b05ae8c77b40b30fe7abaab8
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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refactor(versal-net): use the generic GIC driver

With the introduction of USE_GIC_DRIVER, platforms no longer have to do
their own GIC management for basic PSCI-related operations. Previously a
half

refactor(versal-net): use the generic GIC driver

With the introduction of USE_GIC_DRIVER, platforms no longer have to do
their own GIC management for basic PSCI-related operations. Previously a
half-measure was possible by using plat_gicv3_base.c to get semi-generic
helpers which versal_net uses.

Since USE_GIC_DRIVER is based on plat_gicv3_base.c, convert the platform
to use that so its code is more generic. Expected benefits are slightly
better performance around calling the gic hooks on cpu suspend and less
platform code.

Change-Id: I8e8a92fd4111e4a83c7a34bc5255d924bc54e769
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(v

Merge changes from topic "xlnx_fix_plat_single_ret" into integration

* changes:
fix(versal2): modify function to have single return
fix(versal-net): modify function to have single return
fix(versal): modify function to have single return
fix(xilinx): modify function to have single return
fix(zynqmp): modify function to have single return
fix(versal-net): add unsigned suffix to match data type
fix(versal): add unsigned suffix to match data type
fix(versal2): add missing curly braces
fix(versal-net): add missing curly braces
fix(zynqmp): add missing curly braces

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fix(versal-net): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to stor

fix(versal-net): modify function to have single return

This corrects the MISRA violation C2012-15.5:
A function should have a single point of exit at the end.
Introduced a temporary variable to store the return value to
ensure single return for the function.

Change-Id: Ib8b3339f32031a3657f6c349763a20a99fd828e7
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_set_freq" into integration

* changes:
refactor(xilinx): move plat_get_syscnt_freq2 to common file
refactor(versal-net): rename VERSAL_NET_IOU_SCNTRS register to ge

Merge changes from topic "xlnx_set_freq" into integration

* changes:
refactor(xilinx): move plat_get_syscnt_freq2 to common file
refactor(versal-net): rename VERSAL_NET_IOU_SCNTRS register to generic
fix(versal-net): setup counter frequency
fix(versal): initialize cntfrq_el0 register

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fix(versal-net): setup counter frequency

Refactor the system counter configuration into the
syscnt_freq_config_setup() function as it involves timestamp and
system counter configuration, which requi

fix(versal-net): setup counter frequency

Refactor the system counter configuration into the
syscnt_freq_config_setup() function as it involves timestamp and
system counter configuration, which requires early configuration for
clock setup and read the value of the IOU_SCNTRS_BASE_FREQ register
using mmio_read_32() to determine the counter frequency.

If the counter frequency is zero, the system will set the default CPU
clocks constants in TF-A and displays message. However, if the counter
frequency is non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.

The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0() exceeds the expiration count, reached to timeout.

After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.

Change-Id: Ib9ed3493d22f23c832f8bb7d11c4f727fe1ebe3c
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support

Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
feat(versal): add tsp support
refactor(xilinx): add generic TSP makefile
chore(zynqmp): reorganize tsp code into common path
refactor(xilinx): rename platform function to generic name

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refactor(xilinx): rename platform function to generic name

Refactor two platform specific functions, plat_versal_get_mmap() and
plat_versal_net_get_mmap(), to use a more generic function name
plat_g

refactor(xilinx): rename platform function to generic name

Refactor two platform specific functions, plat_versal_get_mmap() and
plat_versal_net_get_mmap(), to use a more generic function name
plat_get_mmap(). The function can be used in the common code to
obtain memory region.

Change-Id: I3eeb24aff217eef30af60a7742cbebe9d3b2edce
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "xlnx_dtb_console" into integration

* changes:
feat(versal-net): retrieval of console information from dtb
feat(versal): retrieval of console information from dtb
refa

Merge changes from topic "xlnx_dtb_console" into integration

* changes:
feat(versal-net): retrieval of console information from dtb
feat(versal): retrieval of console information from dtb
refactor(xilinx): create generic function for clock retrieval
feat(zynqmp): retrieval of console information from dtb

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refactor(xilinx): create generic function for clock retrieval

Refactors the code in the AMD-Xilinx platform for Versal and Versal NET
to create a more generic function for obtaining clock signals
fr

refactor(xilinx): create generic function for clock retrieval

Refactors the code in the AMD-Xilinx platform for Versal and Versal NET
to create a more generic function for obtaining clock signals
from the platform. The new function get_uart_clk is specific to each
platform and providing greater flexibility for clock signal retrieval
in various parts of the codebase.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Iff67315339b2651c9bea73af0d89fcbad2bb332a

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Merge "style(xilinx): replace ARM by Arm in copyrights" into integration

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.

Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "set-wake-source-for-versal-net" into integration

* changes:
refactor(xilinx): move enum to common place
fix(xilinx): fix misra defects
fix(xilinx): remove unnecessary

Merge changes from topic "set-wake-source-for-versal-net" into integration

* changes:
refactor(xilinx): move enum to common place
fix(xilinx): fix misra defects
fix(xilinx): remove unnecessary condition
feat(versal): replace irq array with switch case
feat(versal-net): add support for set wakeup source
refactor(versal): move set wake src fn to common place

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Merge "refactor(xilinx): move pm_defs.h to common place" into integration

refactor(xilinx): move enum to common place

Moved IOCTL enum from ZynqMP to common place so that it can be used
for all the platforms.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Cha

refactor(xilinx): move enum to common place

Moved IOCTL enum from ZynqMP to common place so that it can be used
for all the platforms.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6ad992da30f2def9f46c8ba79753d79ed00fe024

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refactor(xilinx): move pm_defs.h to common place

Moved pm_defs.h file to common place so that it can be used for
Versal NET and ZynqMP. Also moved common code from zynqmp_pm_defs.h to
common place.

refactor(xilinx): move pm_defs.h to common place

Moved pm_defs.h file to common place so that it can be used for
Versal NET and ZynqMP. Also moved common code from zynqmp_pm_defs.h to
common place.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2ee1e72258c6052cdd6467cdbcf4009afb98da49

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Merge changes from topic "xilinx-versal-net" into integration

* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP s

Merge changes from topic "xilinx-versal-net" into integration

* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC

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feat(versal-net): add support for platform management

Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.

Signed-off-by

feat(versal-net): add support for platform management

Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If2b2941c868bc9b0850d7f3adb81eac0e660c149

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feat(versal-net): add support for Xilinx Versal NET platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx P

feat(versal-net): add support for Xilinx Versal NET platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410

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