1*1d333e69SMichal Simek/* 2*1d333e69SMichal Simek * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*1d333e69SMichal Simek * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4*1d333e69SMichal Simek * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. 5*1d333e69SMichal Simek * 6*1d333e69SMichal Simek * SPDX-License-Identifier: BSD-3-Clause 7*1d333e69SMichal Simek */ 8*1d333e69SMichal Simek 9*1d333e69SMichal Simek#ifndef PLAT_MACROS_S 10*1d333e69SMichal Simek#define PLAT_MACROS_S 11*1d333e69SMichal Simek 12*1d333e69SMichal Simek#include <drivers/arm/gic_common.h> 13*1d333e69SMichal Simek#include <drivers/arm/gicv2.h> 14*1d333e69SMichal Simek#include <drivers/arm/gicv3.h> 15*1d333e69SMichal Simek 16*1d333e69SMichal Simek#include "../include/platform_def.h" 17*1d333e69SMichal Simek 18*1d333e69SMichal Simek.section .rodata.gic_reg_name, "aS" 19*1d333e69SMichal Simek/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 20*1d333e69SMichal Simekgicc_regs: 21*1d333e69SMichal Simek .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 22*1d333e69SMichal Simek 23*1d333e69SMichal Simek/* Applicable only to GICv3 with SRE enabled */ 24*1d333e69SMichal Simekicc_regs: 25*1d333e69SMichal Simek .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 26*1d333e69SMichal Simek 27*1d333e69SMichal Simek/* Registers common to both GICv2 and GICv3 */ 28*1d333e69SMichal Simekgicd_pend_reg: 29*1d333e69SMichal Simek .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 30*1d333e69SMichal Simeknewline: 31*1d333e69SMichal Simek .asciz "\n" 32*1d333e69SMichal Simekspacer: 33*1d333e69SMichal Simek .asciz ":\t\t0x" 34*1d333e69SMichal Simek 35*1d333e69SMichal Simek /* --------------------------------------------- 36*1d333e69SMichal Simek * The below utility macro prints out relevant GIC 37*1d333e69SMichal Simek * registers whenever an unhandled exception is 38*1d333e69SMichal Simek * taken in BL31 on Versal NET platform. 39*1d333e69SMichal Simek * Expects: GICD base in x16, GICC base in x17 40*1d333e69SMichal Simek * Clobbers: x0 - x10, sp 41*1d333e69SMichal Simek * --------------------------------------------- 42*1d333e69SMichal Simek */ 43*1d333e69SMichal Simek .macro versal_net_print_gic_regs 44*1d333e69SMichal Simek /* Check for GICv3 system register access */ 45*1d333e69SMichal Simek mrs x7, id_aa64pfr0_el1 46*1d333e69SMichal Simek ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 47*1d333e69SMichal Simek cmp x7, #1 48*1d333e69SMichal Simek b.ne print_gicv2 49*1d333e69SMichal Simek 50*1d333e69SMichal Simek /* Check for SRE enable */ 51*1d333e69SMichal Simek mrs x8, ICC_SRE_EL3 52*1d333e69SMichal Simek tst x8, #ICC_SRE_SRE_BIT 53*1d333e69SMichal Simek b.eq print_gicv2 54*1d333e69SMichal Simek 55*1d333e69SMichal Simek /* Load the icc reg list to x6 */ 56*1d333e69SMichal Simek adr x6, icc_regs 57*1d333e69SMichal Simek /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 58*1d333e69SMichal Simek mrs x8, ICC_HPPIR0_EL1 59*1d333e69SMichal Simek mrs x9, ICC_HPPIR1_EL1 60*1d333e69SMichal Simek mrs x10, ICC_CTLR_EL3 61*1d333e69SMichal Simek /* Store to the crash buf and print to console */ 62*1d333e69SMichal Simek bl str_in_crash_buf_print 63*1d333e69SMichal Simek b print_gic_common 64*1d333e69SMichal Simek 65*1d333e69SMichal Simekprint_gicv2: 66*1d333e69SMichal Simek /* Load the gicc reg list to x6 */ 67*1d333e69SMichal Simek adr x6, gicc_regs 68*1d333e69SMichal Simek /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 69*1d333e69SMichal Simek ldr w8, [x17, #GICC_HPPIR] 70*1d333e69SMichal Simek ldr w9, [x17, #GICC_AHPPIR] 71*1d333e69SMichal Simek ldr w10, [x17, #GICC_CTLR] 72*1d333e69SMichal Simek /* Store to the crash buf and print to console */ 73*1d333e69SMichal Simek bl str_in_crash_buf_print 74*1d333e69SMichal Simek 75*1d333e69SMichal Simekprint_gic_common: 76*1d333e69SMichal Simek /* Print the GICD_ISPENDR regs */ 77*1d333e69SMichal Simek add x7, x16, #GICD_ISPENDR 78*1d333e69SMichal Simek adr x4, gicd_pend_reg 79*1d333e69SMichal Simek bl asm_print_str 80*1d333e69SMichal Simekgicd_ispendr_loop: 81*1d333e69SMichal Simek sub x4, x7, x16 82*1d333e69SMichal Simek cmp x4, #0x280 83*1d333e69SMichal Simek b.eq exit_print_gic_regs 84*1d333e69SMichal Simek bl asm_print_hex 85*1d333e69SMichal Simek 86*1d333e69SMichal Simek adr x4, spacer 87*1d333e69SMichal Simek bl asm_print_str 88*1d333e69SMichal Simek 89*1d333e69SMichal Simek ldr x4, [x7], #8 90*1d333e69SMichal Simek bl asm_print_hex 91*1d333e69SMichal Simek 92*1d333e69SMichal Simek adr x4, newline 93*1d333e69SMichal Simek bl asm_print_str 94*1d333e69SMichal Simek b gicd_ispendr_loop 95*1d333e69SMichal Simekexit_print_gic_regs: 96*1d333e69SMichal Simek .endm 97*1d333e69SMichal Simek 98*1d333e69SMichal Simek /* --------------------------------------------- 99*1d333e69SMichal Simek * The below required platform porting macro 100*1d333e69SMichal Simek * prints out relevant GIC and CCI registers 101*1d333e69SMichal Simek * whenever an unhandled exception is taken in 102*1d333e69SMichal Simek * BL31. 103*1d333e69SMichal Simek * Clobbers: x0 - x10, x16, x17, sp 104*1d333e69SMichal Simek * --------------------------------------------- 105*1d333e69SMichal Simek */ 106*1d333e69SMichal Simek .macro plat_crash_print_regs 107*1d333e69SMichal Simek /* 108*1d333e69SMichal Simek * Empty for now to handle more platforms variant. 109*1d333e69SMichal Simek * Uncomment it when versions are stable 110*1d333e69SMichal Simek */ 111*1d333e69SMichal Simek /* 112*1d333e69SMichal Simek mov_imm x17, PLAT_VERSAL_NET_GICD_BASE 113*1d333e69SMichal Simek mov_imm x16, PLAT_VERSAL_NET_GICR_BASE 114*1d333e69SMichal Simek versal_net_print_gic_regs 115*1d333e69SMichal Simek */ 116*1d333e69SMichal Simek .endm 117*1d333e69SMichal Simek 118*1d333e69SMichal Simek#endif /* PLAT_MACROS_S */ 119