1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <plat_arm.h> 19 #include <plat_console.h> 20 #include <plat_clkfunc.h> 21 22 #include <plat_fdt.h> 23 #include <plat_private.h> 24 #include <plat_startup.h> 25 #include <pm_api_sys.h> 26 #include <pm_client.h> 27 #include <pm_ipi.h> 28 #include <versal_net_def.h> 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 /* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 */ 39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 assert(sec_state_is_valid(type)); 42 43 if (type == NON_SECURE) { 44 return &bl33_image_ep_info; 45 } 46 47 return &bl32_image_ep_info; 48 } 49 50 /* 51 * Set the build time defaults,if we can't find any config data. 52 */ 53 static inline void bl31_set_default_config(void) 54 { 55 bl32_image_ep_info.pc = BL32_BASE; 56 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 57 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 58 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 59 DISABLE_ALL_EXCEPTIONS); 60 } 61 62 /* 63 * Perform any BL31 specific platform actions. Here is an opportunity to copy 64 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 65 * are lost (potentially). This needs to be done before the MMU is initialized 66 * so that the memory layout can be used while creating page tables. 67 */ 68 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 69 u_register_t arg2, u_register_t arg3) 70 { 71 #if !(TFA_NO_PM) 72 uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0}; 73 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 74 enum pm_ret_status ret_status; 75 #endif /* !(TFA_NO_PM) */ 76 77 board_detection(); 78 79 switch (platform_id) { 80 case VERSAL_NET_SPP: 81 cpu_clock = 1000000; 82 break; 83 case VERSAL_NET_EMU: 84 cpu_clock = 3660000; 85 break; 86 case VERSAL_NET_QEMU: 87 /* Random values now */ 88 cpu_clock = 100000000; 89 break; 90 case VERSAL_NET_SILICON: 91 cpu_clock = 100000000; 92 break; 93 default: 94 panic(); 95 } 96 97 syscnt_freq_config_setup(); 98 99 set_cnt_freq(); 100 101 setup_console(); 102 103 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 104 platform_version / 10U, platform_version % 10U); 105 106 /* Initialize the platform config for future decision making */ 107 versal_net_config_setup(); 108 109 /* 110 * Do initial security configuration to allow DRAM/device access. On 111 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but 112 * other platforms might have more programmable security devices 113 * present. 114 */ 115 116 /* Populate common information for BL32 and BL33 */ 117 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 118 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 119 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 120 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 121 #if !(TFA_NO_PM) 122 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 123 (uintptr_t)buff >> 32U, (uintptr_t)buff, max_size); 124 125 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 126 if (ret_status == PM_RET_SUCCESS) { 127 enum xbl_handoff xbl_ret; 128 129 tfa_handoff_addr = (uintptr_t)&buff; 130 131 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, 132 tfa_handoff_addr); 133 if (xbl_ret != XBL_HANDOFF_SUCCESS) { 134 ERROR("BL31: PLM to TF-A handover failed %u\n", xbl_ret); 135 panic(); 136 } 137 138 INFO("BL31: PLM to TF-A handover success\n"); 139 140 /* 141 * The BL32 load address is indicated as 0x0 in the handoff 142 * parameters, which is different from the default/user-provided 143 * load address of 0x60000000 but the flags are correctly 144 * configured. Consequently, in this scenario, set the PC 145 * to the requested BL32_BASE address. 146 */ 147 148 /* TODO: Remove the following check once this is fixed from PLM */ 149 if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) { 150 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 151 } 152 } else { 153 INFO("BL31: setting up default configs\n"); 154 155 bl31_set_default_config(); 156 } 157 #else 158 bl31_set_default_config(); 159 #endif /* !(TFA_NO_PM) */ 160 161 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 162 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 163 } 164 165 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 166 167 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 168 { 169 static uint32_t index; 170 uint32_t i; 171 172 /* Validate 'handler' and 'id' parameters */ 173 if (handler == NULL || index >= MAX_INTR_EL3) { 174 return -EINVAL; 175 } 176 177 /* Check if a handler has already been registered */ 178 for (i = 0; i < index; i++) { 179 if (id == type_el3_interrupt_table[i].id) { 180 return -EALREADY; 181 } 182 } 183 184 type_el3_interrupt_table[index].id = id; 185 type_el3_interrupt_table[index].handler = handler; 186 187 index++; 188 189 return 0; 190 } 191 192 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 193 void *handle, void *cookie) 194 { 195 uint32_t intr_id; 196 uint32_t i; 197 interrupt_type_handler_t handler = NULL; 198 199 intr_id = plat_ic_get_pending_interrupt_id(); 200 201 for (i = 0; i < MAX_INTR_EL3; i++) { 202 if (intr_id == type_el3_interrupt_table[i].id) { 203 handler = type_el3_interrupt_table[i].handler; 204 } 205 } 206 207 if (handler != NULL) { 208 handler(intr_id, flags, handle, cookie); 209 } 210 211 return 0; 212 } 213 214 void bl31_platform_setup(void) 215 { 216 prepare_dtb(); 217 218 /* Initialize the gic cpu and distributor interfaces */ 219 plat_versal_net_gic_driver_init(); 220 plat_versal_net_gic_init(); 221 } 222 223 void bl31_plat_runtime_setup(void) 224 { 225 uint64_t flags = 0; 226 int32_t rc; 227 228 set_interrupt_rm_flag(flags, NON_SECURE); 229 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 230 rdo_el3_interrupt_handler, flags); 231 if (rc != 0) { 232 panic(); 233 } 234 235 console_switch_state(CONSOLE_FLAG_RUNTIME); 236 } 237 238 /* 239 * Perform the very early platform specific architectural setup here. 240 */ 241 void bl31_plat_arch_setup(void) 242 { 243 const mmap_region_t bl_regions[] = { 244 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 245 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 246 MT_MEMORY | MT_RW | MT_NS), 247 #endif 248 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 249 MT_MEMORY | MT_RW | MT_SECURE), 250 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 251 MT_CODE | MT_SECURE), 252 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 253 MT_RO_DATA | MT_SECURE), 254 {0} 255 }; 256 257 setup_page_tables(bl_regions, plat_get_mmap()); 258 enable_mmu(0); 259 } 260