1 /* 2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <plat_arm.h> 19 #include <plat_console.h> 20 #include <plat_clkfunc.h> 21 22 #include <plat_fdt.h> 23 #include <plat_private.h> 24 #include <plat_startup.h> 25 #include <pm_api_sys.h> 26 #include <pm_client.h> 27 #include <pm_ipi.h> 28 #include <versal_net_def.h> 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 /* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 */ 39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 assert(sec_state_is_valid(type)); 42 43 if (type == NON_SECURE) { 44 return &bl33_image_ep_info; 45 } 46 47 return &bl32_image_ep_info; 48 } 49 50 /* 51 * Set the build time defaults,if we can't find any config data. 52 */ 53 static inline void bl31_set_default_config(void) 54 { 55 bl32_image_ep_info.pc = BL32_BASE; 56 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 57 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 58 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 59 DISABLE_ALL_EXCEPTIONS); 60 } 61 62 /* Define read and write function for clusterbusqos register */ 63 DEFINE_RENAME_SYSREG_RW_FUNCS(cluster_bus_qos, S3_0_C15_C4_4) 64 65 static void versal_net_setup_qos(void) 66 { 67 int ret; 68 69 ret = read_cluster_bus_qos(); 70 INFO("BL31: default cluster bus qos: 0x%x\n", ret); 71 write_cluster_bus_qos(0); 72 ret = read_cluster_bus_qos(); 73 INFO("BL31: cluster bus qos written: 0x%x\n", ret); 74 } 75 76 /* 77 * Perform any BL31 specific platform actions. Here is an opportunity to copy 78 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 79 * are lost (potentially). This needs to be done before the MMU is initialized 80 * so that the memory layout can be used while creating page tables. 81 */ 82 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 83 u_register_t arg2, u_register_t arg3) 84 { 85 #if !(TFA_NO_PM) 86 uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0}; 87 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 88 enum pm_ret_status ret_status; 89 #endif /* !(TFA_NO_PM) */ 90 91 board_detection(); 92 93 switch (platform_id) { 94 case VERSAL_NET_SPP: 95 cpu_clock = 1000000; 96 break; 97 case VERSAL_NET_EMU: 98 cpu_clock = 3660000; 99 break; 100 case VERSAL_NET_QEMU: 101 /* Random values now */ 102 cpu_clock = 100000000; 103 break; 104 case VERSAL_NET_SILICON: 105 cpu_clock = 100000000; 106 break; 107 default: 108 panic(); 109 } 110 111 syscnt_freq_config_setup(); 112 113 set_cnt_freq(); 114 115 setup_console(); 116 117 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 118 platform_version / 10U, platform_version % 10U); 119 120 versal_net_setup_qos(); 121 122 /* Initialize the platform config for future decision making */ 123 versal_net_config_setup(); 124 125 /* 126 * Do initial security configuration to allow DRAM/device access. On 127 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but 128 * other platforms might have more programmable security devices 129 * present. 130 */ 131 132 /* Populate common information for BL32 and BL33 */ 133 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 134 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 135 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 136 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 137 #if !(TFA_NO_PM) 138 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 139 (uintptr_t)buff >> 32U, (uintptr_t)buff, max_size); 140 141 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 142 if (ret_status == PM_RET_SUCCESS) { 143 enum xbl_handoff xbl_ret; 144 145 tfa_handoff_addr = (uintptr_t)&buff; 146 147 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, 148 tfa_handoff_addr); 149 if (xbl_ret != XBL_HANDOFF_SUCCESS) { 150 ERROR("BL31: PLM to TF-A handover failed %u\n", xbl_ret); 151 panic(); 152 } 153 154 INFO("BL31: PLM to TF-A handover success\n"); 155 156 } else { 157 INFO("BL31: setting up default configs\n"); 158 159 bl31_set_default_config(); 160 } 161 #else 162 bl31_set_default_config(); 163 #endif /* !(TFA_NO_PM) */ 164 165 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 166 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 167 } 168 169 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 170 171 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 172 { 173 static uint32_t index; 174 uint32_t i; 175 176 /* Validate 'handler' and 'id' parameters */ 177 if (handler == NULL || index >= MAX_INTR_EL3) { 178 return -EINVAL; 179 } 180 181 /* Check if a handler has already been registered */ 182 for (i = 0; i < index; i++) { 183 if (id == type_el3_interrupt_table[i].id) { 184 return -EALREADY; 185 } 186 } 187 188 type_el3_interrupt_table[index].id = id; 189 type_el3_interrupt_table[index].handler = handler; 190 191 index++; 192 193 return 0; 194 } 195 196 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 197 void *handle, void *cookie) 198 { 199 uint32_t intr_id; 200 uint32_t i; 201 interrupt_type_handler_t handler = NULL; 202 203 intr_id = plat_ic_get_pending_interrupt_id(); 204 205 for (i = 0; i < MAX_INTR_EL3; i++) { 206 if (intr_id == type_el3_interrupt_table[i].id) { 207 handler = type_el3_interrupt_table[i].handler; 208 } 209 } 210 211 if (handler != NULL) { 212 handler(intr_id, flags, handle, cookie); 213 } 214 215 return 0; 216 } 217 218 void bl31_platform_setup(void) 219 { 220 prepare_dtb(); 221 222 /* Initialize the gic cpu and distributor interfaces */ 223 plat_arm_gic_driver_init(); 224 plat_arm_gic_init(); 225 } 226 227 void bl31_plat_runtime_setup(void) 228 { 229 uint64_t flags = 0; 230 int32_t rc; 231 232 set_interrupt_rm_flag(flags, NON_SECURE); 233 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 234 rdo_el3_interrupt_handler, flags); 235 if (rc != 0) { 236 panic(); 237 } 238 } 239 240 /* 241 * Perform the very early platform specific architectural setup here. 242 */ 243 void bl31_plat_arch_setup(void) 244 { 245 const mmap_region_t bl_regions[] = { 246 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 247 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 248 MT_MEMORY | MT_RW | MT_NS), 249 #endif 250 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 251 MT_MEMORY | MT_RW | MT_SECURE), 252 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 253 MT_CODE | MT_SECURE), 254 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 255 MT_RO_DATA | MT_SECURE), 256 {0} 257 }; 258 259 setup_page_tables(bl_regions, plat_get_mmap()); 260 enable_mmu(0); 261 } 262