1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/fdt_fixup.h> 16 #include <common/fdt_wrappers.h> 17 #include <drivers/arm/dcc.h> 18 #include <drivers/arm/pl011.h> 19 #include <drivers/console.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <libfdt.h> 23 #include <plat/common/platform.h> 24 #include <plat_arm.h> 25 26 #include <plat_private.h> 27 #include <plat_startup.h> 28 #include <versal_net_def.h> 29 30 static entry_point_info_t bl32_image_ep_info; 31 static entry_point_info_t bl33_image_ep_info; 32 33 /* 34 * Return a pointer to the 'entry_point_info' structure of the next image for 35 * the security state specified. BL33 corresponds to the non-secure image type 36 * while BL32 corresponds to the secure image type. A NULL pointer is returned 37 * if the image does not exist. 38 */ 39 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 40 { 41 assert(sec_state_is_valid(type)); 42 43 if (type == NON_SECURE) { 44 return &bl33_image_ep_info; 45 } 46 47 return &bl32_image_ep_info; 48 } 49 50 /* 51 * Set the build time defaults,if we can't find any config data. 52 */ 53 static inline void bl31_set_default_config(void) 54 { 55 bl32_image_ep_info.pc = BL32_BASE; 56 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 57 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 58 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 59 DISABLE_ALL_EXCEPTIONS); 60 } 61 62 /* 63 * Perform any BL31 specific platform actions. Here is an opportunity to copy 64 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 65 * are lost (potentially). This needs to be done before the MMU is initialized 66 * so that the memory layout can be used while creating page tables. 67 */ 68 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 69 u_register_t arg2, u_register_t arg3) 70 { 71 uint32_t uart_clock; 72 int32_t rc; 73 74 board_detection(); 75 76 switch (platform_id) { 77 case VERSAL_NET_SPP: 78 cpu_clock = 1000000; 79 uart_clock = 1000000; 80 break; 81 case VERSAL_NET_EMU: 82 cpu_clock = 3660000; 83 uart_clock = 25000000; 84 break; 85 case VERSAL_NET_QEMU: 86 /* Random values now */ 87 cpu_clock = 100000000; 88 uart_clock = 25000000; 89 break; 90 case VERSAL_NET_SILICON: 91 cpu_clock = 100000000; 92 uart_clock = 100000000; 93 break; 94 default: 95 panic(); 96 } 97 98 if (VERSAL_NET_CONSOLE_IS(pl011_0) || VERSAL_NET_CONSOLE_IS(pl011_1)) { 99 static console_t versal_net_runtime_console; 100 101 /* Initialize the console to provide early debug support */ 102 rc = console_pl011_register(VERSAL_NET_UART_BASE, uart_clock, 103 VERSAL_NET_UART_BAUDRATE, 104 &versal_net_runtime_console); 105 if (rc == 0) { 106 panic(); 107 } 108 109 console_set_scope(&versal_net_runtime_console, CONSOLE_FLAG_BOOT | 110 CONSOLE_FLAG_RUNTIME); 111 } else if (VERSAL_NET_CONSOLE_IS(dcc)) { 112 /* Initialize the dcc console for debug. 113 * dcc is over jtag and does not configures uart0 or uart1. 114 */ 115 rc = console_dcc_register(); 116 if (rc == 0) { 117 panic(); 118 } 119 } 120 121 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 122 platform_version / 10U, platform_version % 10U); 123 124 /* Initialize the platform config for future decision making */ 125 versal_net_config_setup(); 126 127 /* 128 * Do initial security configuration to allow DRAM/device access. On 129 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but 130 * other platforms might have more programmable security devices 131 * present. 132 */ 133 134 /* Populate common information for BL32 and BL33 */ 135 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 136 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 137 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 138 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 139 140 bl31_set_default_config(); 141 142 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 143 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 144 } 145 146 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 147 148 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 149 { 150 static uint32_t index; 151 uint32_t i; 152 153 /* Validate 'handler' and 'id' parameters */ 154 if (handler == NULL || index >= MAX_INTR_EL3) { 155 return -EINVAL; 156 } 157 158 /* Check if a handler has already been registered */ 159 for (i = 0; i < index; i++) { 160 if (id == type_el3_interrupt_table[i].id) { 161 return -EALREADY; 162 } 163 } 164 165 type_el3_interrupt_table[index].id = id; 166 type_el3_interrupt_table[index].handler = handler; 167 168 index++; 169 170 return 0; 171 } 172 173 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 174 void *handle, void *cookie) 175 { 176 uint32_t intr_id; 177 uint32_t i; 178 interrupt_type_handler_t handler = NULL; 179 180 intr_id = plat_ic_get_pending_interrupt_id(); 181 182 for (i = 0; i < MAX_INTR_EL3; i++) { 183 if (intr_id == type_el3_interrupt_table[i].id) { 184 handler = type_el3_interrupt_table[i].handler; 185 } 186 } 187 188 if (handler != NULL) { 189 handler(intr_id, flags, handle, cookie); 190 } 191 192 return 0; 193 } 194 195 void bl31_platform_setup(void) 196 { 197 /* Initialize the gic cpu and distributor interfaces */ 198 plat_versal_net_gic_driver_init(); 199 plat_versal_net_gic_init(); 200 } 201 202 void bl31_plat_runtime_setup(void) 203 { 204 uint64_t flags = 0; 205 int32_t rc; 206 207 set_interrupt_rm_flag(flags, NON_SECURE); 208 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 209 rdo_el3_interrupt_handler, flags); 210 if (rc != 0) { 211 panic(); 212 } 213 } 214 215 /* 216 * Perform the very early platform specific architectural setup here. 217 */ 218 void bl31_plat_arch_setup(void) 219 { 220 const mmap_region_t bl_regions[] = { 221 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 222 MT_MEMORY | MT_RW | MT_SECURE), 223 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 224 MT_CODE | MT_SECURE), 225 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 226 MT_RO_DATA | MT_SECURE), 227 {0} 228 }; 229 230 setup_page_tables(bl_regions, plat_versal_net_get_mmap()); 231 enable_mmu(0); 232 } 233