1 /* 2 * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <common/ep_info.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <drivers/generic_delay_timer.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <plat/common/platform.h> 16 #include <plat_common.h> 17 #include <plat_ipi.h> 18 #include <pm_api_sys.h> 19 #include <pm_defs.h> 20 21 #include <plat_private.h> 22 #include <versal_net_def.h> 23 24 uint32_t platform_id, platform_version; 25 26 /* 27 * Table of regions to map using the MMU. 28 * This doesn't include TZRAM as the 'mem_layout' argument passed to 29 * configure_mmu_elx() will give the available subset of that, 30 */ 31 const mmap_region_t plat_versal_net_mmap[] = { 32 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 33 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 34 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 35 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 36 MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 37 { 0 } 38 }; 39 40 const mmap_region_t *plat_get_mmap(void) 41 { 42 return plat_versal_net_mmap; 43 } 44 45 /* For saving cpu clock for certain platform */ 46 uint32_t cpu_clock; 47 48 const char *board_name_decode(void) 49 { 50 const char *platform; 51 52 switch (platform_id) { 53 case VERSAL_NET_SPP: 54 platform = "IPP"; 55 break; 56 case VERSAL_NET_EMU: 57 platform = "EMU"; 58 break; 59 case VERSAL_NET_SILICON: 60 platform = "Silicon"; 61 break; 62 case VERSAL_NET_QEMU: 63 platform = "QEMU"; 64 break; 65 default: 66 platform = "Unknown"; 67 } 68 69 return platform; 70 } 71 72 void board_detection(void) 73 { 74 uint32_t version_type; 75 76 version_type = mmio_read_32(PMC_TAP_VERSION); 77 platform_id = FIELD_GET(PLATFORM_MASK, version_type); 78 platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version_type); 79 80 if (platform_id == VERSAL_NET_QEMU_COSIM) { 81 platform_id = VERSAL_NET_QEMU; 82 } 83 84 if ((platform_id == VERSAL_NET_SPP) || 85 (platform_id == VERSAL_NET_EMU) || 86 (platform_id == VERSAL_NET_QEMU)) { 87 /* 88 * 9 is diff for 89 * 0 means 0.9 version 90 * 1 means 1.0 version 91 * 2 means 1.1 version 92 * etc, 93 */ 94 platform_version += 9U; 95 } 96 97 /* Make sure that console is setup to see this message */ 98 VERBOSE("Platform id: %d version: %d.%d\n", platform_id, 99 platform_version / 10U, platform_version % 10U); 100 } 101 102 uint32_t get_uart_clk(void) 103 { 104 uint32_t uart_clock; 105 106 switch (platform_id) { 107 case VERSAL_NET_SPP: 108 uart_clock = 1000000; 109 break; 110 case VERSAL_NET_EMU: 111 uart_clock = 25000000; 112 break; 113 case VERSAL_NET_QEMU: 114 uart_clock = 25000000; 115 break; 116 case VERSAL_NET_SILICON: 117 uart_clock = 100000000; 118 break; 119 default: 120 panic(); 121 } 122 123 return uart_clock; 124 } 125 126 void versal_net_config_setup(void) 127 { 128 generic_delay_timer_init(); 129 130 #if (TFA_NO_PM == 0) 131 /* Configure IPI data for versal_net */ 132 versal_net_ipi_config_table_init(); 133 #endif 134 } 135 136 void syscnt_freq_config_setup(void) 137 { 138 uint32_t val; 139 uintptr_t crl_base, iou_scntrs_base, psx_base; 140 141 crl_base = VERSAL_NET_CRL; 142 iou_scntrs_base = IOU_SCNTRS_BASE; 143 psx_base = PSX_CRF; 144 145 /* Reset for system timestamp generator in FPX */ 146 mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0); 147 148 /* Global timer init - Program time stamp reference clk */ 149 val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET); 150 val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; 151 mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val); 152 153 /* Clear reset of timestamp reg */ 154 mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0); 155 156 /* Program freq register in System counter and enable system counter. */ 157 mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET, 158 cpu_clock); 159 mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET, 160 IOU_SCNTRS_CONTROL_EN); 161 } 162 163 /* 164 * Get bootmode register value via IPI call. 165 */ 166 #if DEBUG 167 void get_boot_mode(uint32_t *mode) 168 { 169 enum pm_ret_status ret_status; 170 171 if (mode != NULL) { 172 ret_status = pm_handle_eemi_call(SECURE, PM_IOCTL, CRP_BOOT_MODE_REG_NODE, 173 IOCTL_READ_REG, CRP_BOOT_MODE_REG_OFFSET, 174 0, 0, mode); 175 176 if (ret_status == PM_RET_SUCCESS) { 177 INFO("bootmode: %u\n", *mode); 178 } else { 179 *mode = BOOT_MODE_INVALID; 180 INFO("Failed to retrieve boot mode reg value via IPI.\n"); 181 } 182 } 183 184 return; 185 } 186 #endif 187