1 /* 2 * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <common/debug.h> 10 #include <common/runtime_svc.h> 11 #include <drivers/generic_delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <plat/common/platform.h> 15 #include <plat_common.h> 16 #include <plat_ipi.h> 17 18 #include <plat_private.h> 19 #include <versal_net_def.h> 20 21 uint32_t platform_id, platform_version; 22 23 /* 24 * Table of regions to map using the MMU. 25 * This doesn't include TZRAM as the 'mem_layout' argument passed to 26 * configure_mmu_elx() will give the available subset of that, 27 */ 28 const mmap_region_t plat_versal_net_mmap[] = { 29 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 31 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 32 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 33 MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 34 { 0 } 35 }; 36 37 const mmap_region_t *plat_get_mmap(void) 38 { 39 return plat_versal_net_mmap; 40 } 41 42 /* For saving cpu clock for certain platform */ 43 uint32_t cpu_clock; 44 45 const char *board_name_decode(void) 46 { 47 const char *platform; 48 49 switch (platform_id) { 50 case VERSAL_NET_SPP: 51 platform = "IPP"; 52 break; 53 case VERSAL_NET_EMU: 54 platform = "EMU"; 55 break; 56 case VERSAL_NET_SILICON: 57 platform = "Silicon"; 58 break; 59 case VERSAL_NET_QEMU: 60 platform = "QEMU"; 61 break; 62 default: 63 platform = "Unknown"; 64 } 65 66 return platform; 67 } 68 69 void board_detection(void) 70 { 71 uint32_t version_type; 72 73 version_type = mmio_read_32(PMC_TAP_VERSION); 74 platform_id = FIELD_GET(PLATFORM_MASK, version_type); 75 platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version_type); 76 77 if (platform_id == VERSAL_NET_QEMU_COSIM) { 78 platform_id = VERSAL_NET_QEMU; 79 } 80 81 if ((platform_id == VERSAL_NET_SPP) || 82 (platform_id == VERSAL_NET_EMU) || 83 (platform_id == VERSAL_NET_QEMU)) { 84 /* 85 * 9 is diff for 86 * 0 means 0.9 version 87 * 1 means 1.0 version 88 * 2 means 1.1 version 89 * etc, 90 */ 91 platform_version += 9U; 92 } 93 94 /* Make sure that console is setup to see this message */ 95 VERBOSE("Platform id: %d version: %d.%d\n", platform_id, 96 platform_version / 10U, platform_version % 10U); 97 } 98 99 uint32_t get_uart_clk(void) 100 { 101 uint32_t uart_clock; 102 103 switch (platform_id) { 104 case VERSAL_NET_SPP: 105 uart_clock = 1000000; 106 break; 107 case VERSAL_NET_EMU: 108 uart_clock = 25000000; 109 break; 110 case VERSAL_NET_QEMU: 111 uart_clock = 25000000; 112 break; 113 case VERSAL_NET_SILICON: 114 uart_clock = 100000000; 115 break; 116 default: 117 panic(); 118 } 119 120 return uart_clock; 121 } 122 123 void versal_net_config_setup(void) 124 { 125 generic_delay_timer_init(); 126 127 #if (TFA_NO_PM == 0) 128 /* Configure IPI data for versal_net */ 129 versal_net_ipi_config_table_init(); 130 #endif 131 } 132 133 void syscnt_freq_config_setup(void) 134 { 135 uint32_t val; 136 uintptr_t crl_base, iou_scntrs_base, psx_base; 137 138 crl_base = VERSAL_NET_CRL; 139 iou_scntrs_base = IOU_SCNTRS_BASE; 140 psx_base = PSX_CRF; 141 142 /* Reset for system timestamp generator in FPX */ 143 mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0); 144 145 /* Global timer init - Program time stamp reference clk */ 146 val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET); 147 val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; 148 mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val); 149 150 /* Clear reset of timestamp reg */ 151 mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0); 152 153 /* Program freq register in System counter and enable system counter. */ 154 mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET, 155 cpu_clock); 156 mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET, 157 IOU_SCNTRS_CONTROL_EN); 158 } 159 160