1*f91c3cb1SSiva Durga Prasad Paladugu# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 2*f91c3cb1SSiva Durga Prasad Paladugu# 3*f91c3cb1SSiva Durga Prasad Paladugu# SPDX-License-Identifier: BSD-3-Clause 4*f91c3cb1SSiva Durga Prasad Paladugu 5*f91c3cb1SSiva Durga Prasad Paladuguoverride PROGRAMMABLE_RESET_ADDRESS := 1 6*f91c3cb1SSiva Durga Prasad PaladuguPSCI_EXTENDED_STATE_ID := 1 7*f91c3cb1SSiva Durga Prasad PaladuguA53_DISABLE_NON_TEMPORAL_HINT := 0 8*f91c3cb1SSiva Durga Prasad PaladuguSEPARATE_CODE_AND_RODATA := 1 9*f91c3cb1SSiva Durga Prasad Paladuguoverride RESET_TO_BL31 := 1 10*f91c3cb1SSiva Durga Prasad PaladuguPL011_GENERIC_UART := 1 11*f91c3cb1SSiva Durga Prasad PaladuguMULTI_CONSOLE_API := 1 12*f91c3cb1SSiva Durga Prasad Paladugu 13*f91c3cb1SSiva Durga Prasad Paladuguifdef VERSAL_ATF_MEM_BASE 14*f91c3cb1SSiva Durga Prasad Paladugu $(eval $(call add_define,VERSAL_ATF_MEM_BASE)) 15*f91c3cb1SSiva Durga Prasad Paladugu 16*f91c3cb1SSiva Durga Prasad Paladugu ifndef VERSAL_ATF_MEM_SIZE 17*f91c3cb1SSiva Durga Prasad Paladugu $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE") 18*f91c3cb1SSiva Durga Prasad Paladugu endif 19*f91c3cb1SSiva Durga Prasad Paladugu $(eval $(call add_define,VERSAL_ATF_MEM_SIZE)) 20*f91c3cb1SSiva Durga Prasad Paladugu 21*f91c3cb1SSiva Durga Prasad Paladugu ifdef VERSAL_ATF_MEM_PROGBITS_SIZE 22*f91c3cb1SSiva Durga Prasad Paladugu $(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE)) 23*f91c3cb1SSiva Durga Prasad Paladugu endif 24*f91c3cb1SSiva Durga Prasad Paladuguendif 25*f91c3cb1SSiva Durga Prasad Paladugu 26*f91c3cb1SSiva Durga Prasad Paladuguifdef VERSAL_BL32_MEM_BASE 27*f91c3cb1SSiva Durga Prasad Paladugu $(eval $(call add_define,VERSAL_BL32_MEM_BASE)) 28*f91c3cb1SSiva Durga Prasad Paladugu 29*f91c3cb1SSiva Durga Prasad Paladugu ifndef VERSAL_BL32_MEM_SIZE 30*f91c3cb1SSiva Durga Prasad Paladugu $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE") 31*f91c3cb1SSiva Durga Prasad Paladugu endif 32*f91c3cb1SSiva Durga Prasad Paladugu $(eval $(call add_define,VERSAL_BL32_MEM_SIZE)) 33*f91c3cb1SSiva Durga Prasad Paladuguendif 34*f91c3cb1SSiva Durga Prasad Paladugu 35*f91c3cb1SSiva Durga Prasad PaladuguVERSAL_PLATFORM ?= versal_virt 36*f91c3cb1SSiva Durga Prasad Paladugu$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM})) 37*f91c3cb1SSiva Durga Prasad Paladugu 38*f91c3cb1SSiva Durga Prasad PaladuguVERSAL_CONSOLE ?= pl011 39*f91c3cb1SSiva Durga Prasad Paladugu$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE})) 40*f91c3cb1SSiva Durga Prasad Paladugu 41*f91c3cb1SSiva Durga Prasad PaladuguPLAT_INCLUDES := -Iplat/xilinx/versal/include/ 42*f91c3cb1SSiva Durga Prasad Paladugu 43*f91c3cb1SSiva Durga Prasad PaladuguPLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ 44*f91c3cb1SSiva Durga Prasad Paladugu lib/xlat_tables/aarch64/xlat_tables.c \ 45*f91c3cb1SSiva Durga Prasad Paladugu drivers/delay_timer/delay_timer.c \ 46*f91c3cb1SSiva Durga Prasad Paladugu drivers/delay_timer/generic_delay_timer.c \ 47*f91c3cb1SSiva Durga Prasad Paladugu drivers/arm/gic/common/gic_common.c \ 48*f91c3cb1SSiva Durga Prasad Paladugu drivers/arm/gic/v3/gicv3_main.c \ 49*f91c3cb1SSiva Durga Prasad Paladugu drivers/arm/gic/v3/gicv3_helpers.c \ 50*f91c3cb1SSiva Durga Prasad Paladugu drivers/arm/pl011/aarch64/pl011_console.S \ 51*f91c3cb1SSiva Durga Prasad Paladugu plat/common/plat_gicv3.c \ 52*f91c3cb1SSiva Durga Prasad Paladugu plat/xilinx/versal/aarch64/versal_helpers.S \ 53*f91c3cb1SSiva Durga Prasad Paladugu plat/xilinx/versal/aarch64/versal_common.c 54*f91c3cb1SSiva Durga Prasad Paladugu 55*f91c3cb1SSiva Durga Prasad PaladuguBL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 56*f91c3cb1SSiva Durga Prasad Paladugu lib/cpus/aarch64/cortex_a72.S \ 57*f91c3cb1SSiva Durga Prasad Paladugu plat/common/plat_psci_common.c \ 58*f91c3cb1SSiva Durga Prasad Paladugu plat/xilinx/versal/bl31_versal_setup.c \ 59*f91c3cb1SSiva Durga Prasad Paladugu plat/xilinx/versal/plat_psci.c \ 60*f91c3cb1SSiva Durga Prasad Paladugu plat/xilinx/versal/plat_versal.c \ 61*f91c3cb1SSiva Durga Prasad Paladugu plat/xilinx/versal/plat_topology.c \ 62*f91c3cb1SSiva Durga Prasad Paladugu plat/xilinx/versal/sip_svc_setup.c \ 63*f91c3cb1SSiva Durga Prasad Paladugu plat/xilinx/versal/versal_gicv3.c 64