xref: /rk3399_ARM-atf/plat/xilinx/versal/platform.mk (revision ade92a64e4d2fbb5f246e6ad891465d10e0d9b26)
1619bc13eSMichal Simek# Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
2a92681d9SJay Buddhabhatti# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
3f91c3cb1SSiva Durga Prasad Paladugu#
4f91c3cb1SSiva Durga Prasad Paladugu# SPDX-License-Identifier: BSD-3-Clause
5f91c3cb1SSiva Durga Prasad Paladugu
6f91c3cb1SSiva Durga Prasad Paladuguoverride PROGRAMMABLE_RESET_ADDRESS := 1
7f91c3cb1SSiva Durga Prasad PaladuguPSCI_EXTENDED_STATE_ID := 1
8f91c3cb1SSiva Durga Prasad PaladuguA53_DISABLE_NON_TEMPORAL_HINT := 0
9f91c3cb1SSiva Durga Prasad PaladuguSEPARATE_CODE_AND_RODATA := 1
10f91c3cb1SSiva Durga Prasad Paladuguoverride RESET_TO_BL31 := 1
11f91c3cb1SSiva Durga Prasad PaladuguPL011_GENERIC_UART := 1
12654bd99dSVenkatesh Yadav AbbarapuIPI_CRC_CHECK := 0
13302b4dfbSVenkatesh Yadav AbbarapuHARDEN_SLS_ALL := 0
14*ade92a64SJay BuddhabhattiCPU_PWRDWN_SGI ?= 6
15*ade92a64SJay Buddhabhatti$(eval $(call add_define_val,CPU_PWR_DOWN_REQ_INTR,ARM_IRQ_SEC_SGI_${CPU_PWRDWN_SGI}))
16f91c3cb1SSiva Durga Prasad Paladugu
17769446a6SMichal Simek# A72 Erratum for SoC
18769446a6SMichal SimekERRATA_A72_859971 := 1
19769446a6SMichal SimekERRATA_A72_1319367 := 1
20769446a6SMichal Simek
21f91c3cb1SSiva Durga Prasad Paladuguifdef VERSAL_ATF_MEM_BASE
22f91c3cb1SSiva Durga Prasad Paladugu    $(eval $(call add_define,VERSAL_ATF_MEM_BASE))
23f91c3cb1SSiva Durga Prasad Paladugu
24f91c3cb1SSiva Durga Prasad Paladugu    ifndef VERSAL_ATF_MEM_SIZE
25f91c3cb1SSiva Durga Prasad Paladugu        $(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
26f91c3cb1SSiva Durga Prasad Paladugu    endif
27f91c3cb1SSiva Durga Prasad Paladugu    $(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
28f91c3cb1SSiva Durga Prasad Paladugu
29f91c3cb1SSiva Durga Prasad Paladugu    ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
30f91c3cb1SSiva Durga Prasad Paladugu        $(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE))
31f91c3cb1SSiva Durga Prasad Paladugu    endif
32f91c3cb1SSiva Durga Prasad Paladuguendif
33f91c3cb1SSiva Durga Prasad Paladugu
34f91c3cb1SSiva Durga Prasad Paladuguifdef VERSAL_BL32_MEM_BASE
35f91c3cb1SSiva Durga Prasad Paladugu    $(eval $(call add_define,VERSAL_BL32_MEM_BASE))
36f91c3cb1SSiva Durga Prasad Paladugu
37f91c3cb1SSiva Durga Prasad Paladugu    ifndef VERSAL_BL32_MEM_SIZE
38f91c3cb1SSiva Durga Prasad Paladugu        $(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
39f91c3cb1SSiva Durga Prasad Paladugu    endif
40f91c3cb1SSiva Durga Prasad Paladugu    $(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
41f91c3cb1SSiva Durga Prasad Paladuguendif
42f91c3cb1SSiva Durga Prasad Paladugu
43654bd99dSVenkatesh Yadav Abbarapuifdef IPI_CRC_CHECK
44654bd99dSVenkatesh Yadav Abbarapu    $(eval $(call add_define,IPI_CRC_CHECK))
45654bd99dSVenkatesh Yadav Abbarapuendif
46654bd99dSVenkatesh Yadav Abbarapu
477b9f0cfdSSiva Durga Prasad PaladuguVERSAL_PLATFORM ?= silicon
48f91c3cb1SSiva Durga Prasad Paladugu$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
49f91c3cb1SSiva Durga Prasad Paladugu
5056d1857eSAmit Nagalifdef XILINX_OF_BOARD_DTB_ADDR
5156d1857eSAmit Nagal$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
5256d1857eSAmit Nagalendif
5356d1857eSAmit Nagal
547ca7fb1bSAmit NagalPLAT_XLAT_TABLES_DYNAMIC := 0
557ca7fb1bSAmit Nagalifeq (${PLAT_XLAT_TABLES_DYNAMIC},1)
567ca7fb1bSAmit Nagal$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
577ca7fb1bSAmit Nagalendif
587ca7fb1bSAmit Nagal
590375188aSAmit Nagal# enable assert() for release/debug builds
600375188aSAmit NagalENABLE_ASSERTIONS := 1
610375188aSAmit Nagal
625a8ffeabSTejas PatelPLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
635a8ffeabSTejas Patel				-Iplat/xilinx/common/include/			\
646e2f0d10SWendy Liang				-Iplat/xilinx/common/ipi_mailbox_service/	\
65c73a90e5STejas Patel				-Iplat/xilinx/versal/include/			\
66c73a90e5STejas Patel				-Iplat/xilinx/versal/pm_service/
67f91c3cb1SSiva Durga Prasad Paladugu
6856d1857eSAmit Nagalinclude lib/libfdt/libfdt.mk
69a6ea06f5SAlexei Fedorov# Include GICv3 driver files
70a6ea06f5SAlexei Fedorovinclude drivers/arm/gic/v3/gicv3.mk
710e9f54e5SMichal Simekinclude lib/xlat_tables_v2/xlat_tables.mk
72a6ea06f5SAlexei Fedorov
730e9f54e5SMichal SimekPLAT_BL_COMMON_SOURCES	:= 	drivers/arm/dcc/dcc_console.c			\
74f91c3cb1SSiva Durga Prasad Paladugu				drivers/delay_timer/delay_timer.c		\
75f91c3cb1SSiva Durga Prasad Paladugu				drivers/delay_timer/generic_delay_timer.c	\
76a6ea06f5SAlexei Fedorov				${GICV3_SOURCES}				\
77f91c3cb1SSiva Durga Prasad Paladugu				drivers/arm/pl011/aarch64/pl011_console.S	\
782cc97771SAmbroise Vincent				plat/common/aarch64/crash_console_helpers.S	\
795a8ffeabSTejas Patel				plat/arm/common/arm_cci.c			\
8031ce893eSVenkatesh Yadav Abbarapu				plat/arm/common/arm_common.c			\
81f91c3cb1SSiva Durga Prasad Paladugu				plat/common/plat_gicv3.c			\
82f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/aarch64/versal_helpers.S	\
830e9f54e5SMichal Simek				plat/xilinx/versal/aarch64/versal_common.c	\
840e9f54e5SMichal Simek				${XLAT_TABLES_LIB_SRCS}
85f91c3cb1SSiva Durga Prasad Paladugu
860b25f404SVenkatesh Yadav AbbarapuVERSAL_CONSOLE	?=	pl011
870b25f404SVenkatesh Yadav Abbarapuifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc))
880b25f404SVenkatesh Yadav Abbarapuelse
890b25f404SVenkatesh Yadav Abbarapu  $(error "Please define VERSAL_CONSOLE")
900b25f404SVenkatesh Yadav Abbarapuendif
910b25f404SVenkatesh Yadav Abbarapu
920b25f404SVenkatesh Yadav Abbarapu$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
930b25f404SVenkatesh Yadav Abbarapu
945a8ffeabSTejas PatelBL31_SOURCES		+=	drivers/arm/cci/cci.c				\
95f91c3cb1SSiva Durga Prasad Paladugu				lib/cpus/aarch64/cortex_a72.S			\
967c36fbccSPrasad Kummari				common/fdt_wrappers.c                           \
97f91c3cb1SSiva Durga Prasad Paladugu				plat/common/plat_psci_common.c			\
98c73a90e5STejas Patel				plat/xilinx/common/ipi.c			\
9956d1857eSAmit Nagal				plat/xilinx/common/plat_fdt.c			\
1007c36fbccSPrasad Kummari				plat/xilinx/common/plat_console.c               \
101f000744eSPrasad Kummari				plat/xilinx/common/plat_clkfunc.c               \
10231ce893eSVenkatesh Yadav Abbarapu				plat/xilinx/common/plat_startup.c		\
1036e2f0d10SWendy Liang				plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
104c73a90e5STejas Patel				plat/xilinx/common/pm_service/pm_ipi.c		\
105a92681d9SJay Buddhabhatti				plat/xilinx/common/pm_service/pm_api_sys.c	\
106a92681d9SJay Buddhabhatti				plat/xilinx/common/pm_service/pm_svc_main.c	\
107079c6e24SAkshay Belsare				plat/xilinx/common/versal.c			\
108f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/bl31_versal_setup.c		\
109f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/plat_psci.c			\
110f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/plat_versal.c		\
111f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/plat_topology.c		\
112f91c3cb1SSiva Durga Prasad Paladugu				plat/xilinx/versal/sip_svc_setup.c		\
113c73a90e5STejas Patel				plat/xilinx/versal/versal_gicv3.c		\
114c73a90e5STejas Patel				plat/xilinx/versal/versal_ipi.c			\
11556d1857eSAmit Nagal				plat/xilinx/versal/pm_service/pm_client.c	\
11656d1857eSAmit Nagal				common/fdt_fixup.c				\
11756d1857eSAmit Nagal				${LIBFDT_SRCS}
118302b4dfbSVenkatesh Yadav Abbarapu
119302b4dfbSVenkatesh Yadav Abbarapuifeq ($(HARDEN_SLS_ALL), 1)
120302b4dfbSVenkatesh Yadav AbbarapuTF_CFLAGS_aarch64      +=      -mharden-sls=all
121302b4dfbSVenkatesh Yadav Abbarapuendif
122d766f994SPrasad Kummari
123d766f994SPrasad Kummariifeq (${ERRATA_ABI_SUPPORT}, 1)
124d766f994SPrasad Kummari# enable the cpu macros for errata abi interface
125d766f994SPrasad KummariCORTEX_A72_H_INC	:= 1
126d766f994SPrasad Kummari$(eval $(call add_define, CORTEX_A72_H_INC))
127d766f994SPrasad Kummariendif
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