1 /* 2 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <plat_common.h> 13 #include "versal_def.h" 14 15 /******************************************************************************* 16 * Generic platform constants 17 ******************************************************************************/ 18 19 /* Size of cacheable stacks */ 20 #ifndef PLATFORM_STACK_SIZE 21 #define PLATFORM_STACK_SIZE U(0x440) 22 #endif 23 24 #define PLATFORM_CORE_COUNT U(2) 25 #define PLAT_MAX_PWR_LVL U(1) 26 #define PLAT_MAX_RET_STATE U(1) 27 #define PLAT_MAX_OFF_STATE U(2) 28 29 /******************************************************************************* 30 * BL31 specific defines. 31 ******************************************************************************/ 32 /* 33 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 34 * present). BL31_BASE is calculated using the current BL31 debug size plus a 35 * little space for growth. 36 */ 37 #ifndef VERSAL_ATF_MEM_BASE 38 # define BL31_BASE U(0xfffe0000) 39 # define BL31_LIMIT U(0x100000000) 40 #else 41 # define BL31_BASE U(VERSAL_ATF_MEM_BASE) 42 # define BL31_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE) 43 # ifdef VERSAL_ATF_MEM_PROGBITS_SIZE 44 # define BL31_PROGBITS_LIMIT U(VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE) 45 # endif 46 #endif 47 48 /******************************************************************************* 49 * BL32 specific defines. 50 ******************************************************************************/ 51 #ifndef VERSAL_BL32_MEM_BASE 52 # define BL32_BASE U(0x60000000) 53 # define BL32_LIMIT U(0x80000000) 54 #else 55 # define BL32_BASE U(VERSAL_BL32_MEM_BASE) 56 # define BL32_LIMIT U(VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE) 57 #endif 58 59 /******************************************************************************* 60 * BL33 specific defines. 61 ******************************************************************************/ 62 #ifndef PRELOADED_BL33_BASE 63 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 64 #else 65 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 66 #endif 67 68 /******************************************************************************* 69 * HIGH and LOW DDR MAX definitions 70 ******************************************************************************/ 71 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 72 #define PLAT_DDR_HIGHMEM_MAX U(0x100000000) 73 74 /******************************************************************************* 75 * TSP specific defines. 76 ******************************************************************************/ 77 #define TSP_SEC_MEM_BASE BL32_BASE 78 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 79 80 /* ID of the secure physical generic timer interrupt used by the TSP */ 81 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 82 83 /******************************************************************************* 84 * Platform specific page table and MMU setup constants 85 ******************************************************************************/ 86 87 #if (BL31_BASE >= (1ULL << 32U)) 88 /* Address range in High DDR and HBM memory range */ 89 #define PLAT_ADDR_SPACE_SHIFT U(42) 90 #else 91 /* Address range in OCM and Low DDR memory range */ 92 #define PLAT_ADDR_SPACE_SHIFT U(32) 93 #endif 94 95 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << PLAT_ADDR_SPACE_SHIFT) 96 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << PLAT_ADDR_SPACE_SHIFT) 97 98 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 99 100 #define PLAT_OCM_BASE U(0xFFFE0000) 101 #define PLAT_OCM_LIMIT U(0xFFFFFFFF) 102 103 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 104 105 #ifndef MAX_MMAP_REGIONS 106 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 107 #define MAX_MMAP_REGIONS 9 108 #else 109 #define MAX_MMAP_REGIONS 8 110 #endif 111 #endif 112 113 #ifndef MAX_XLAT_TABLES 114 #if !IS_TFA_IN_OCM(BL31_BASE) 115 #define MAX_XLAT_TABLES 9 116 #else 117 #define MAX_XLAT_TABLES 5 118 #endif 119 #endif 120 121 #define CACHE_WRITEBACK_SHIFT 6 122 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 123 124 #define PLAT_ARM_GICD_BASE U(0xF9000000) 125 #define PLAT_ARM_GICR_BASE U(0xF9080000) 126 127 /* 128 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 129 * terminology. On a GICv2 system or mode, the lists will be merged and treated 130 * as Group 0 interrupts. 131 */ 132 #define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER 133 #define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER 134 #define PLAT_VERSAL_IPI_IRQ U(62) 135 136 #define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \ 137 INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 138 GIC_INTR_CFG_LEVEL) 139 140 #define PLAT_VERSAL_G0_IRQ_PROPS(grp) \ 141 INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \ 142 GIC_INTR_CFG_EDGE), \ 143 INTR_PROP_DESC(CPU_PWR_DOWN_REQ_INTR, GIC_HIGHEST_SEC_PRIORITY, grp, \ 144 GIC_INTR_CFG_EDGE) 145 146 #define IRQ_MAX 142U 147 148 #endif /* PLATFORM_DEF_H */ 149