1*c73a90e5STejas Patel /* 2*c73a90e5STejas Patel * Copyright (c) 2019, Xilinx, Inc. All rights reserved. 3*c73a90e5STejas Patel * 4*c73a90e5STejas Patel * SPDX-License-Identifier: BSD-3-Clause 5*c73a90e5STejas Patel */ 6*c73a90e5STejas Patel 7*c73a90e5STejas Patel /* Versal IPI management enums and defines */ 8*c73a90e5STejas Patel 9*c73a90e5STejas Patel #ifndef PLAT_IPI_H 10*c73a90e5STejas Patel #define PLAT_IPI_H 11*c73a90e5STejas Patel 12*c73a90e5STejas Patel #include <ipi.h> 13*c73a90e5STejas Patel #include <stdint.h> 14*c73a90e5STejas Patel 15*c73a90e5STejas Patel /********************************************************************* 16*c73a90e5STejas Patel * IPI agent IDs macros 17*c73a90e5STejas Patel ********************************************************************/ 18*c73a90e5STejas Patel #define IPI_ID_PMC 1U 19*c73a90e5STejas Patel #define IPI_ID_APU 2U 20*c73a90e5STejas Patel #define IPI_ID_RPU0 3U 21*c73a90e5STejas Patel #define IPI_ID_RPU1 4U 22*c73a90e5STejas Patel #define IPI_ID_3 5U 23*c73a90e5STejas Patel #define IPI_ID_4 6U 24*c73a90e5STejas Patel #define IPI_ID_5 7U 25*c73a90e5STejas Patel 26*c73a90e5STejas Patel /********************************************************************* 27*c73a90e5STejas Patel * IPI message buffers 28*c73a90e5STejas Patel ********************************************************************/ 29*c73a90e5STejas Patel #define IPI_BUFFER_BASEADDR 0xFF3F0000U 30*c73a90e5STejas Patel 31*c73a90e5STejas Patel #define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) 32*c73a90e5STejas Patel #define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U) 33*c73a90e5STejas Patel 34*c73a90e5STejas Patel #define IPI_BUFFER_TARGET_APU_OFFSET 0x0U 35*c73a90e5STejas Patel #define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U 36*c73a90e5STejas Patel 37*c73a90e5STejas Patel #define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE 38*c73a90e5STejas Patel #define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE 39*c73a90e5STejas Patel 40*c73a90e5STejas Patel #define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET 41*c73a90e5STejas Patel #define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET 42*c73a90e5STejas Patel 43*c73a90e5STejas Patel #define IPI_BUFFER_MAX_WORDS 8 44*c73a90e5STejas Patel 45*c73a90e5STejas Patel #define IPI_BUFFER_REQ_OFFSET 0x0U 46*c73a90e5STejas Patel #define IPI_BUFFER_RESP_OFFSET 0x20U 47*c73a90e5STejas Patel 48*c73a90e5STejas Patel /********************************************************************* 49*c73a90e5STejas Patel * Platform specific IPI API declarations 50*c73a90e5STejas Patel ********************************************************************/ 51*c73a90e5STejas Patel 52*c73a90e5STejas Patel /* Configure IPI table for versal */ 53*c73a90e5STejas Patel void versal_ipi_config_table_init(void); 54*c73a90e5STejas Patel 55*c73a90e5STejas Patel #endif /* PLAT_IPI_H */ 56