1c73a90e5STejas Patel /* 2*bfd06265SMichal Simek * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 3*bfd06265SMichal Simek * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 4c73a90e5STejas Patel * 5c73a90e5STejas Patel * SPDX-License-Identifier: BSD-3-Clause 6c73a90e5STejas Patel */ 7c73a90e5STejas Patel 8c73a90e5STejas Patel /* Versal IPI management enums and defines */ 9c73a90e5STejas Patel 10c73a90e5STejas Patel #ifndef PLAT_IPI_H 11c73a90e5STejas Patel #define PLAT_IPI_H 12c73a90e5STejas Patel 13c73a90e5STejas Patel #include <ipi.h> 14c73a90e5STejas Patel #include <stdint.h> 15c73a90e5STejas Patel 16c73a90e5STejas Patel /********************************************************************* 17c73a90e5STejas Patel * IPI agent IDs macros 18c73a90e5STejas Patel ********************************************************************/ 19c73a90e5STejas Patel #define IPI_ID_PMC 1U 20c73a90e5STejas Patel #define IPI_ID_APU 2U 21c73a90e5STejas Patel #define IPI_ID_RPU0 3U 22c73a90e5STejas Patel #define IPI_ID_RPU1 4U 23c73a90e5STejas Patel #define IPI_ID_3 5U 24c73a90e5STejas Patel #define IPI_ID_4 6U 25c73a90e5STejas Patel #define IPI_ID_5 7U 26c73a90e5STejas Patel 27c73a90e5STejas Patel /********************************************************************* 28c73a90e5STejas Patel * IPI message buffers 29c73a90e5STejas Patel ********************************************************************/ 30c73a90e5STejas Patel #define IPI_BUFFER_BASEADDR 0xFF3F0000U 31c73a90e5STejas Patel 32*bfd06265SMichal Simek #define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + 0x400U) 33*bfd06265SMichal Simek #define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + 0x200U) 34c73a90e5STejas Patel 35*bfd06265SMichal Simek #define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U 36*bfd06265SMichal Simek #define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x40U 37c73a90e5STejas Patel 38c73a90e5STejas Patel #define IPI_BUFFER_MAX_WORDS 8 39c73a90e5STejas Patel 40c73a90e5STejas Patel #define IPI_BUFFER_REQ_OFFSET 0x0U 41c73a90e5STejas Patel #define IPI_BUFFER_RESP_OFFSET 0x20U 42c73a90e5STejas Patel 43c73a90e5STejas Patel /********************************************************************* 44c73a90e5STejas Patel * Platform specific IPI API declarations 45c73a90e5STejas Patel ********************************************************************/ 46c73a90e5STejas Patel 47c73a90e5STejas Patel /* Configure IPI table for versal */ 48c73a90e5STejas Patel void versal_ipi_config_table_init(void); 49c73a90e5STejas Patel 50b2258ce3SMichal Simek /* IPI registers and bitfields */ 51b2258ce3SMichal Simek #define PMC_REG_BASE U(0xFF320000) 52b2258ce3SMichal Simek #define PMC_IPI_TRIG_BIT (1U << 1U) 53b2258ce3SMichal Simek #define IPI0_REG_BASE U(0xFF330000) 54b2258ce3SMichal Simek #define IPI0_TRIG_BIT (1U << 2U) 55b2258ce3SMichal Simek #define IPI1_REG_BASE U(0xFF340000) 56b2258ce3SMichal Simek #define IPI1_TRIG_BIT (1U << 3U) 57b2258ce3SMichal Simek #define IPI2_REG_BASE U(0xFF350000) 58b2258ce3SMichal Simek #define IPI2_TRIG_BIT (1U << 4U) 59b2258ce3SMichal Simek #define IPI3_REG_BASE U(0xFF360000) 60b2258ce3SMichal Simek #define IPI3_TRIG_BIT (1U << 5U) 61b2258ce3SMichal Simek #define IPI4_REG_BASE U(0xFF370000) 62b2258ce3SMichal Simek #define IPI4_TRIG_BIT (1U << 5U) 63b2258ce3SMichal Simek #define IPI5_REG_BASE U(0xFF380000) 64b2258ce3SMichal Simek #define IPI5_TRIG_BIT (1U << 6U) 65b2258ce3SMichal Simek 66c73a90e5STejas Patel #endif /* PLAT_IPI_H */ 67