1c73a90e5STejas Patel /* 2c73a90e5STejas Patel * Copyright (c) 2019, Xilinx, Inc. All rights reserved. 3c73a90e5STejas Patel * 4c73a90e5STejas Patel * SPDX-License-Identifier: BSD-3-Clause 5c73a90e5STejas Patel */ 6c73a90e5STejas Patel 7c73a90e5STejas Patel /* Versal IPI management enums and defines */ 8c73a90e5STejas Patel 9c73a90e5STejas Patel #ifndef PLAT_IPI_H 10c73a90e5STejas Patel #define PLAT_IPI_H 11c73a90e5STejas Patel 12c73a90e5STejas Patel #include <ipi.h> 13c73a90e5STejas Patel #include <stdint.h> 14c73a90e5STejas Patel 15c73a90e5STejas Patel /********************************************************************* 16c73a90e5STejas Patel * IPI agent IDs macros 17c73a90e5STejas Patel ********************************************************************/ 18c73a90e5STejas Patel #define IPI_ID_PMC 1U 19c73a90e5STejas Patel #define IPI_ID_APU 2U 20c73a90e5STejas Patel #define IPI_ID_RPU0 3U 21c73a90e5STejas Patel #define IPI_ID_RPU1 4U 22c73a90e5STejas Patel #define IPI_ID_3 5U 23c73a90e5STejas Patel #define IPI_ID_4 6U 24c73a90e5STejas Patel #define IPI_ID_5 7U 25c73a90e5STejas Patel 26c73a90e5STejas Patel /********************************************************************* 27c73a90e5STejas Patel * IPI message buffers 28c73a90e5STejas Patel ********************************************************************/ 29c73a90e5STejas Patel #define IPI_BUFFER_BASEADDR 0xFF3F0000U 30c73a90e5STejas Patel 31c73a90e5STejas Patel #define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) 32c73a90e5STejas Patel #define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U) 33c73a90e5STejas Patel 34e1e5b133SRajan Vaja #define IPI_BUFFER_TARGET_APU_OFFSET 0x80U 35c73a90e5STejas Patel #define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U 36c73a90e5STejas Patel 37c73a90e5STejas Patel #define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE 38c73a90e5STejas Patel 39c73a90e5STejas Patel #define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET 40c73a90e5STejas Patel #define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET 41c73a90e5STejas Patel 42c73a90e5STejas Patel #define IPI_BUFFER_MAX_WORDS 8 43c73a90e5STejas Patel 44c73a90e5STejas Patel #define IPI_BUFFER_REQ_OFFSET 0x0U 45c73a90e5STejas Patel #define IPI_BUFFER_RESP_OFFSET 0x20U 46c73a90e5STejas Patel 47c73a90e5STejas Patel /********************************************************************* 48c73a90e5STejas Patel * Platform specific IPI API declarations 49c73a90e5STejas Patel ********************************************************************/ 50c73a90e5STejas Patel 51c73a90e5STejas Patel /* Configure IPI table for versal */ 52c73a90e5STejas Patel void versal_ipi_config_table_init(void); 53c73a90e5STejas Patel 54*b2258ce3SMichal Simek /* IPI registers and bitfields */ 55*b2258ce3SMichal Simek #define PMC_REG_BASE U(0xFF320000) 56*b2258ce3SMichal Simek #define PMC_IPI_TRIG_BIT (1U << 1U) 57*b2258ce3SMichal Simek #define IPI0_REG_BASE U(0xFF330000) 58*b2258ce3SMichal Simek #define IPI0_TRIG_BIT (1U << 2U) 59*b2258ce3SMichal Simek #define IPI1_REG_BASE U(0xFF340000) 60*b2258ce3SMichal Simek #define IPI1_TRIG_BIT (1U << 3U) 61*b2258ce3SMichal Simek #define IPI2_REG_BASE U(0xFF350000) 62*b2258ce3SMichal Simek #define IPI2_TRIG_BIT (1U << 4U) 63*b2258ce3SMichal Simek #define IPI3_REG_BASE U(0xFF360000) 64*b2258ce3SMichal Simek #define IPI3_TRIG_BIT (1U << 5U) 65*b2258ce3SMichal Simek #define IPI4_REG_BASE U(0xFF370000) 66*b2258ce3SMichal Simek #define IPI4_TRIG_BIT (1U << 5U) 67*b2258ce3SMichal Simek #define IPI5_REG_BASE U(0xFF380000) 68*b2258ce3SMichal Simek #define IPI5_TRIG_BIT (1U << 6U) 69*b2258ce3SMichal Simek 70c73a90e5STejas Patel #endif /* PLAT_IPI_H */ 71