xref: /rk3399_ARM-atf/plat/xilinx/versal/aarch64/versal_common.c (revision 26f1534ebdd5c91eb3581eae06dac78ba9043b95)
1 /*
2  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <plat_ipi.h>
8 #include <versal_def.h>
9 #include <plat_private.h>
10 #include <common/debug.h>
11 #include <drivers/generic_delay_timer.h>
12 #include <lib/mmio.h>
13 #include <lib/xlat_tables/xlat_tables.h>
14 #include <plat/common/platform.h>
15 
16 /*
17  * Table of regions to map using the MMU.
18  * This doesn't include TZRAM as the 'mem_layout' argument passed to
19  * configure_mmu_elx() will give the available subset of that,
20  */
21 const mmap_region_t plat_versal_mmap[] = {
22 	MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
23 	MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
24 	MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
25 	{ 0 }
26 };
27 
28 const mmap_region_t *plat_versal_get_mmap(void)
29 {
30 	return plat_versal_mmap;
31 }
32 
33 static void versal_print_platform_name(void)
34 {
35 	NOTICE("ATF running on Xilinx %s\n", PLATFORM_NAME);
36 }
37 
38 void versal_config_setup(void)
39 {
40 	uint32_t val;
41 
42 	/* Configure IPI data for versal */
43 	versal_ipi_config_table_init();
44 
45 	versal_print_platform_name();
46 
47 	mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL,
48 		      VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT |
49 		      (0x20 << VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT));
50 
51 	/* Global timer init - Program time stamp reference clk */
52 	val = mmio_read_32(VERSAL_CRL_TIMESTAMP_REF_CTRL);
53 	val |= VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
54 	mmio_write_32(VERSAL_CRL_TIMESTAMP_REF_CTRL, val);
55 
56 	/* Clear reset of timestamp reg */
57 	mmio_write_32(VERSAL_CRL_RST_TIMESTAMP_OFFSET, 0x0);
58 
59 	/* Program freq register in System counter and enable system counter. */
60 	mmio_write_32(VERSAL_IOU_SCNTRS_BASE_FREQ, VERSAL_CPU_CLOCK);
61 	mmio_write_32(VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG,
62 		      VERSAL_IOU_SCNTRS_CONTROL_EN);
63 
64 	generic_delay_timer_init();
65 }
66 
67 unsigned int plat_get_syscnt_freq2(void)
68 {
69 	return VERSAL_CPU_CLOCK;
70 }
71 
72 uintptr_t plat_get_ns_image_entrypoint(void)
73 {
74 #ifdef PRELOADED_BL33_BASE
75 	return PRELOADED_BL33_BASE;
76 #else
77 	return PLAT_VERSAL_NS_IMAGE_OFFSET;
78 #endif
79 }
80