xref: /rk3399_ARM-atf/plat/xilinx/versal/aarch64/versal_common.c (revision f91c3cb1df7d41122185063453f39dfe90119b5b)
1*f91c3cb1SSiva Durga Prasad Paladugu /*
2*f91c3cb1SSiva Durga Prasad Paladugu  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3*f91c3cb1SSiva Durga Prasad Paladugu  *
4*f91c3cb1SSiva Durga Prasad Paladugu  * SPDX-License-Identifier: BSD-3-Clause
5*f91c3cb1SSiva Durga Prasad Paladugu  */
6*f91c3cb1SSiva Durga Prasad Paladugu 
7*f91c3cb1SSiva Durga Prasad Paladugu #include <debug.h>
8*f91c3cb1SSiva Durga Prasad Paladugu #include <generic_delay_timer.h>
9*f91c3cb1SSiva Durga Prasad Paladugu #include <mmio.h>
10*f91c3cb1SSiva Durga Prasad Paladugu #include <platform.h>
11*f91c3cb1SSiva Durga Prasad Paladugu #include <xlat_tables.h>
12*f91c3cb1SSiva Durga Prasad Paladugu #include "../versal_def.h"
13*f91c3cb1SSiva Durga Prasad Paladugu #include "../versal_private.h"
14*f91c3cb1SSiva Durga Prasad Paladugu 
15*f91c3cb1SSiva Durga Prasad Paladugu /*
16*f91c3cb1SSiva Durga Prasad Paladugu  * Table of regions to map using the MMU.
17*f91c3cb1SSiva Durga Prasad Paladugu  * This doesn't include TZRAM as the 'mem_layout' argument passed to
18*f91c3cb1SSiva Durga Prasad Paladugu  * configure_mmu_elx() will give the available subset of that,
19*f91c3cb1SSiva Durga Prasad Paladugu  */
20*f91c3cb1SSiva Durga Prasad Paladugu const mmap_region_t plat_versal_mmap[] = {
21*f91c3cb1SSiva Durga Prasad Paladugu 	MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
22*f91c3cb1SSiva Durga Prasad Paladugu 	MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
23*f91c3cb1SSiva Durga Prasad Paladugu 	MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
24*f91c3cb1SSiva Durga Prasad Paladugu 	{ 0 }
25*f91c3cb1SSiva Durga Prasad Paladugu };
26*f91c3cb1SSiva Durga Prasad Paladugu 
27*f91c3cb1SSiva Durga Prasad Paladugu const mmap_region_t *plat_versal_get_mmap(void)
28*f91c3cb1SSiva Durga Prasad Paladugu {
29*f91c3cb1SSiva Durga Prasad Paladugu 	return plat_versal_mmap;
30*f91c3cb1SSiva Durga Prasad Paladugu }
31*f91c3cb1SSiva Durga Prasad Paladugu 
32*f91c3cb1SSiva Durga Prasad Paladugu static void versal_print_platform_name(void)
33*f91c3cb1SSiva Durga Prasad Paladugu {
34*f91c3cb1SSiva Durga Prasad Paladugu 	NOTICE("ATF running on Xilinx %s\n", PLATFORM_NAME);
35*f91c3cb1SSiva Durga Prasad Paladugu }
36*f91c3cb1SSiva Durga Prasad Paladugu 
37*f91c3cb1SSiva Durga Prasad Paladugu void versal_config_setup(void)
38*f91c3cb1SSiva Durga Prasad Paladugu {
39*f91c3cb1SSiva Durga Prasad Paladugu 	uint32_t val;
40*f91c3cb1SSiva Durga Prasad Paladugu 
41*f91c3cb1SSiva Durga Prasad Paladugu 	versal_print_platform_name();
42*f91c3cb1SSiva Durga Prasad Paladugu 
43*f91c3cb1SSiva Durga Prasad Paladugu 	mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL,
44*f91c3cb1SSiva Durga Prasad Paladugu 		      VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT |
45*f91c3cb1SSiva Durga Prasad Paladugu 		      (0x20 << VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT));
46*f91c3cb1SSiva Durga Prasad Paladugu 
47*f91c3cb1SSiva Durga Prasad Paladugu 	/* Global timer init - Program time stamp reference clk */
48*f91c3cb1SSiva Durga Prasad Paladugu 	val = mmio_read_32(VERSAL_CRL_TIMESTAMP_REF_CTRL);
49*f91c3cb1SSiva Durga Prasad Paladugu 	val |= VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
50*f91c3cb1SSiva Durga Prasad Paladugu 	mmio_write_32(VERSAL_CRL_TIMESTAMP_REF_CTRL, val);
51*f91c3cb1SSiva Durga Prasad Paladugu 
52*f91c3cb1SSiva Durga Prasad Paladugu 	/* Clear reset of timestamp reg */
53*f91c3cb1SSiva Durga Prasad Paladugu 	mmio_write_32(VERSAL_CRL_RST_TIMESTAMP_OFFSET, 0x0);
54*f91c3cb1SSiva Durga Prasad Paladugu 
55*f91c3cb1SSiva Durga Prasad Paladugu 	/* Program freq register in System counter and enable system counter. */
56*f91c3cb1SSiva Durga Prasad Paladugu 	mmio_write_32(VERSAL_IOU_SCNTRS_BASE_FREQ, VERSAL_CPU_CLOCK);
57*f91c3cb1SSiva Durga Prasad Paladugu 	mmio_write_32(VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG,
58*f91c3cb1SSiva Durga Prasad Paladugu 		      VERSAL_IOU_SCNTRS_CONTROL_EN);
59*f91c3cb1SSiva Durga Prasad Paladugu 
60*f91c3cb1SSiva Durga Prasad Paladugu 	generic_delay_timer_init();
61*f91c3cb1SSiva Durga Prasad Paladugu }
62*f91c3cb1SSiva Durga Prasad Paladugu 
63*f91c3cb1SSiva Durga Prasad Paladugu unsigned int plat_get_syscnt_freq2(void)
64*f91c3cb1SSiva Durga Prasad Paladugu {
65*f91c3cb1SSiva Durga Prasad Paladugu 	return VERSAL_CPU_CLOCK;
66*f91c3cb1SSiva Durga Prasad Paladugu }
67*f91c3cb1SSiva Durga Prasad Paladugu 
68*f91c3cb1SSiva Durga Prasad Paladugu uintptr_t plat_get_ns_image_entrypoint(void)
69*f91c3cb1SSiva Durga Prasad Paladugu {
70*f91c3cb1SSiva Durga Prasad Paladugu #ifdef PRELOADED_BL33_BASE
71*f91c3cb1SSiva Durga Prasad Paladugu 	return PRELOADED_BL33_BASE;
72*f91c3cb1SSiva Durga Prasad Paladugu #else
73*f91c3cb1SSiva Durga Prasad Paladugu 	return PLAT_VERSAL_NS_IMAGE_OFFSET;
74*f91c3cb1SSiva Durga Prasad Paladugu #endif
75*f91c3cb1SSiva Durga Prasad Paladugu }
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