1f91c3cb1SSiva Durga Prasad Paladugu /* 2*d4821739STejas Patel * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3f91c3cb1SSiva Durga Prasad Paladugu * 4f91c3cb1SSiva Durga Prasad Paladugu * SPDX-License-Identifier: BSD-3-Clause 5f91c3cb1SSiva Durga Prasad Paladugu */ 6f91c3cb1SSiva Durga Prasad Paladugu 7*d4821739STejas Patel #include <plat_private.h> 809d40e0eSAntonio Nino Diaz #include <common/debug.h> 909d40e0eSAntonio Nino Diaz #include <drivers/generic_delay_timer.h> 1009d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 1109d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables.h> 1209d40e0eSAntonio Nino Diaz #include <plat/common/platform.h> 13f91c3cb1SSiva Durga Prasad Paladugu #include "../versal_def.h" 14f91c3cb1SSiva Durga Prasad Paladugu 15f91c3cb1SSiva Durga Prasad Paladugu /* 16f91c3cb1SSiva Durga Prasad Paladugu * Table of regions to map using the MMU. 17f91c3cb1SSiva Durga Prasad Paladugu * This doesn't include TZRAM as the 'mem_layout' argument passed to 18f91c3cb1SSiva Durga Prasad Paladugu * configure_mmu_elx() will give the available subset of that, 19f91c3cb1SSiva Durga Prasad Paladugu */ 20f91c3cb1SSiva Durga Prasad Paladugu const mmap_region_t plat_versal_mmap[] = { 21f91c3cb1SSiva Durga Prasad Paladugu MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 22f91c3cb1SSiva Durga Prasad Paladugu MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 23f91c3cb1SSiva Durga Prasad Paladugu MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 24f91c3cb1SSiva Durga Prasad Paladugu { 0 } 25f91c3cb1SSiva Durga Prasad Paladugu }; 26f91c3cb1SSiva Durga Prasad Paladugu 27f91c3cb1SSiva Durga Prasad Paladugu const mmap_region_t *plat_versal_get_mmap(void) 28f91c3cb1SSiva Durga Prasad Paladugu { 29f91c3cb1SSiva Durga Prasad Paladugu return plat_versal_mmap; 30f91c3cb1SSiva Durga Prasad Paladugu } 31f91c3cb1SSiva Durga Prasad Paladugu 32f91c3cb1SSiva Durga Prasad Paladugu static void versal_print_platform_name(void) 33f91c3cb1SSiva Durga Prasad Paladugu { 34f91c3cb1SSiva Durga Prasad Paladugu NOTICE("ATF running on Xilinx %s\n", PLATFORM_NAME); 35f91c3cb1SSiva Durga Prasad Paladugu } 36f91c3cb1SSiva Durga Prasad Paladugu 37f91c3cb1SSiva Durga Prasad Paladugu void versal_config_setup(void) 38f91c3cb1SSiva Durga Prasad Paladugu { 39f91c3cb1SSiva Durga Prasad Paladugu uint32_t val; 40f91c3cb1SSiva Durga Prasad Paladugu 41f91c3cb1SSiva Durga Prasad Paladugu versal_print_platform_name(); 42f91c3cb1SSiva Durga Prasad Paladugu 43f91c3cb1SSiva Durga Prasad Paladugu mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL, 44f91c3cb1SSiva Durga Prasad Paladugu VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT | 45f91c3cb1SSiva Durga Prasad Paladugu (0x20 << VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT)); 46f91c3cb1SSiva Durga Prasad Paladugu 47f91c3cb1SSiva Durga Prasad Paladugu /* Global timer init - Program time stamp reference clk */ 48f91c3cb1SSiva Durga Prasad Paladugu val = mmio_read_32(VERSAL_CRL_TIMESTAMP_REF_CTRL); 49f91c3cb1SSiva Durga Prasad Paladugu val |= VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; 50f91c3cb1SSiva Durga Prasad Paladugu mmio_write_32(VERSAL_CRL_TIMESTAMP_REF_CTRL, val); 51f91c3cb1SSiva Durga Prasad Paladugu 52f91c3cb1SSiva Durga Prasad Paladugu /* Clear reset of timestamp reg */ 53f91c3cb1SSiva Durga Prasad Paladugu mmio_write_32(VERSAL_CRL_RST_TIMESTAMP_OFFSET, 0x0); 54f91c3cb1SSiva Durga Prasad Paladugu 55f91c3cb1SSiva Durga Prasad Paladugu /* Program freq register in System counter and enable system counter. */ 56f91c3cb1SSiva Durga Prasad Paladugu mmio_write_32(VERSAL_IOU_SCNTRS_BASE_FREQ, VERSAL_CPU_CLOCK); 57f91c3cb1SSiva Durga Prasad Paladugu mmio_write_32(VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG, 58f91c3cb1SSiva Durga Prasad Paladugu VERSAL_IOU_SCNTRS_CONTROL_EN); 59f91c3cb1SSiva Durga Prasad Paladugu 60f91c3cb1SSiva Durga Prasad Paladugu generic_delay_timer_init(); 61f91c3cb1SSiva Durga Prasad Paladugu } 62f91c3cb1SSiva Durga Prasad Paladugu 63f91c3cb1SSiva Durga Prasad Paladugu unsigned int plat_get_syscnt_freq2(void) 64f91c3cb1SSiva Durga Prasad Paladugu { 65f91c3cb1SSiva Durga Prasad Paladugu return VERSAL_CPU_CLOCK; 66f91c3cb1SSiva Durga Prasad Paladugu } 67f91c3cb1SSiva Durga Prasad Paladugu 68f91c3cb1SSiva Durga Prasad Paladugu uintptr_t plat_get_ns_image_entrypoint(void) 69f91c3cb1SSiva Durga Prasad Paladugu { 70f91c3cb1SSiva Durga Prasad Paladugu #ifdef PRELOADED_BL33_BASE 71f91c3cb1SSiva Durga Prasad Paladugu return PRELOADED_BL33_BASE; 72f91c3cb1SSiva Durga Prasad Paladugu #else 73f91c3cb1SSiva Durga Prasad Paladugu return PLAT_VERSAL_NS_IMAGE_OFFSET; 74f91c3cb1SSiva Durga Prasad Paladugu #endif 75f91c3cb1SSiva Durga Prasad Paladugu } 76