xref: /rk3399_ARM-atf/plat/xilinx/versal/aarch64/versal_common.c (revision 09ac1ca27c6497cd1e04e108d4d927500d737991)
1f91c3cb1SSiva Durga Prasad Paladugu /*
2619bc13eSMichal Simek  * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
3*09ac1ca2SMaheedhar Bollapalli  * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
4f91c3cb1SSiva Durga Prasad Paladugu  *
5f91c3cb1SSiva Durga Prasad Paladugu  * SPDX-License-Identifier: BSD-3-Clause
6f91c3cb1SSiva Durga Prasad Paladugu  */
7f91c3cb1SSiva Durga Prasad Paladugu 
809d40e0eSAntonio Nino Diaz #include <common/debug.h>
909d40e0eSAntonio Nino Diaz #include <lib/mmio.h>
100e9f54e5SMichal Simek #include <lib/xlat_tables/xlat_tables_v2.h>
1109d40e0eSAntonio Nino Diaz #include <plat/common/platform.h>
12f91c3cb1SSiva Durga Prasad Paladugu 
13079c6e24SAkshay Belsare #include <plat_common.h>
14079c6e24SAkshay Belsare #include <plat_ipi.h>
15079c6e24SAkshay Belsare #include <plat_private.h>
16079c6e24SAkshay Belsare #include <pm_api_sys.h>
17079c6e24SAkshay Belsare #include <versal_def.h>
18079c6e24SAkshay Belsare 
19079c6e24SAkshay Belsare uint32_t platform_id, platform_version;
20*09ac1ca2SMaheedhar Bollapalli uint32_t cpu_clock;
21079c6e24SAkshay Belsare 
22f91c3cb1SSiva Durga Prasad Paladugu /*
23f91c3cb1SSiva Durga Prasad Paladugu  * Table of regions to map using the MMU.
24f91c3cb1SSiva Durga Prasad Paladugu  * This doesn't include TZRAM as the 'mem_layout' argument passed to
25f91c3cb1SSiva Durga Prasad Paladugu  * configure_mmu_elx() will give the available subset of that,
26f91c3cb1SSiva Durga Prasad Paladugu  */
27f91c3cb1SSiva Durga Prasad Paladugu const mmap_region_t plat_versal_mmap[] = {
28f91c3cb1SSiva Durga Prasad Paladugu 	MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
29f91c3cb1SSiva Durga Prasad Paladugu 	MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30f91c3cb1SSiva Durga Prasad Paladugu 	MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
31245d30efSMichal Simek 	MAP_REGION_FLAT(PLAT_ARM_CCI_BASE, PLAT_ARM_CCI_SIZE, MT_DEVICE | MT_RW |
325a8ffeabSTejas Patel 			MT_SECURE),
33f91c3cb1SSiva Durga Prasad Paladugu 	{ 0 }
34f91c3cb1SSiva Durga Prasad Paladugu };
35f91c3cb1SSiva Durga Prasad Paladugu 
3651564354SPrasad Kummari const mmap_region_t *plat_get_mmap(void)
37f91c3cb1SSiva Durga Prasad Paladugu {
38f91c3cb1SSiva Durga Prasad Paladugu 	return plat_versal_mmap;
39f91c3cb1SSiva Durga Prasad Paladugu }
40f91c3cb1SSiva Durga Prasad Paladugu 
41f91c3cb1SSiva Durga Prasad Paladugu void versal_config_setup(void)
42f91c3cb1SSiva Durga Prasad Paladugu {
43c73a90e5STejas Patel 	/* Configure IPI data for versal */
44c73a90e5STejas Patel 	versal_ipi_config_table_init();
45f91c3cb1SSiva Durga Prasad Paladugu }
46f91c3cb1SSiva Durga Prasad Paladugu 
47079c6e24SAkshay Belsare void board_detection(void)
48079c6e24SAkshay Belsare {
49079c6e24SAkshay Belsare 	uint32_t plat_info[2];
50079c6e24SAkshay Belsare 
51079c6e24SAkshay Belsare 	if (pm_get_chipid(plat_info) != PM_RET_SUCCESS) {
52079c6e24SAkshay Belsare 		/* If the call is failed we cannot proceed with further
53079c6e24SAkshay Belsare 		 * setup. TF-A to panic in this situation.
54079c6e24SAkshay Belsare 		 */
55079c6e24SAkshay Belsare 		NOTICE("Failed to read the chip information");
56079c6e24SAkshay Belsare 		panic();
57079c6e24SAkshay Belsare 	}
58079c6e24SAkshay Belsare 
59079c6e24SAkshay Belsare 	platform_id = FIELD_GET(PLATFORM_MASK, plat_info[1]);
60079c6e24SAkshay Belsare 	platform_version = FIELD_GET(PLATFORM_VERSION_MASK, plat_info[1]);
61079c6e24SAkshay Belsare }
62c1e84acaSPrasad Kummari 
63*09ac1ca2SMaheedhar Bollapalli const char *board_name_decode(void)
64*09ac1ca2SMaheedhar Bollapalli {
65*09ac1ca2SMaheedhar Bollapalli 	const char *platform;
66*09ac1ca2SMaheedhar Bollapalli 
67*09ac1ca2SMaheedhar Bollapalli 	switch (platform_id) {
68*09ac1ca2SMaheedhar Bollapalli 	case VERSAL_SPP:
69*09ac1ca2SMaheedhar Bollapalli 		platform = "IPP";
70*09ac1ca2SMaheedhar Bollapalli 		break;
71*09ac1ca2SMaheedhar Bollapalli 	case VERSAL_EMU:
72*09ac1ca2SMaheedhar Bollapalli 		platform = "EMU";
73*09ac1ca2SMaheedhar Bollapalli 		break;
74*09ac1ca2SMaheedhar Bollapalli 	case VERSAL_QEMU:
75*09ac1ca2SMaheedhar Bollapalli 		platform = "QEMU";
76*09ac1ca2SMaheedhar Bollapalli 		break;
77*09ac1ca2SMaheedhar Bollapalli 	case VERSAL_SILICON:
78*09ac1ca2SMaheedhar Bollapalli 		platform = "SILICON";
79*09ac1ca2SMaheedhar Bollapalli 		break;
80*09ac1ca2SMaheedhar Bollapalli 	default:
81*09ac1ca2SMaheedhar Bollapalli 		platform = "unknown";
82*09ac1ca2SMaheedhar Bollapalli 	}
83*09ac1ca2SMaheedhar Bollapalli 
84*09ac1ca2SMaheedhar Bollapalli 	return platform;
85*09ac1ca2SMaheedhar Bollapalli }
86*09ac1ca2SMaheedhar Bollapalli 
87c1e84acaSPrasad Kummari uint32_t get_uart_clk(void)
88c1e84acaSPrasad Kummari {
89*09ac1ca2SMaheedhar Bollapalli 	uint32_t uart_clock;
90*09ac1ca2SMaheedhar Bollapalli 
91*09ac1ca2SMaheedhar Bollapalli 	switch (platform_id) {
92*09ac1ca2SMaheedhar Bollapalli 	case VERSAL_SPP:
93*09ac1ca2SMaheedhar Bollapalli 		uart_clock = 25000000;
94*09ac1ca2SMaheedhar Bollapalli 		break;
95*09ac1ca2SMaheedhar Bollapalli 	case VERSAL_EMU:
96*09ac1ca2SMaheedhar Bollapalli 		uart_clock = 212000;
97*09ac1ca2SMaheedhar Bollapalli 		break;
98*09ac1ca2SMaheedhar Bollapalli 	case VERSAL_QEMU:
99*09ac1ca2SMaheedhar Bollapalli 		uart_clock = 25000000;
100*09ac1ca2SMaheedhar Bollapalli 		break;
101*09ac1ca2SMaheedhar Bollapalli 	case VERSAL_SILICON:
102*09ac1ca2SMaheedhar Bollapalli 		uart_clock = 100000000;
103*09ac1ca2SMaheedhar Bollapalli 		break;
104*09ac1ca2SMaheedhar Bollapalli 	default:
105*09ac1ca2SMaheedhar Bollapalli 		panic();
106*09ac1ca2SMaheedhar Bollapalli 	}
107*09ac1ca2SMaheedhar Bollapalli 
108*09ac1ca2SMaheedhar Bollapalli 	return uart_clock;
109c1e84acaSPrasad Kummari }
110