xref: /rk3399_ARM-atf/plat/xilinx/common/plat_clkfunc.c (revision cc3374ac6342ee9c61c9d51b15a5001eba0922c9)
1f000744eSPrasad Kummari /*
2f000744eSPrasad Kummari  * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
3f000744eSPrasad Kummari  *
4f000744eSPrasad Kummari  * SPDX-License-Identifier: BSD-3-Clause
5f000744eSPrasad Kummari  */
6f000744eSPrasad Kummari #include <common/debug.h>
7*cc3374acSPrasad Kummari #include <lib/mmio.h>
8f000744eSPrasad Kummari #include <plat/common/platform.h>
9f000744eSPrasad Kummari 
10f000744eSPrasad Kummari #include <platform_def.h>
11f000744eSPrasad Kummari #include <plat_private.h>
12f000744eSPrasad Kummari 
13*cc3374acSPrasad Kummari uint32_t plat_get_syscnt_freq2(void)
14*cc3374acSPrasad Kummari {
15*cc3374acSPrasad Kummari 	uint32_t counter_freq = 0;
16*cc3374acSPrasad Kummari 	uint32_t ret = 0;
17*cc3374acSPrasad Kummari 
18*cc3374acSPrasad Kummari 	counter_freq = mmio_read_32(IOU_SCNTRS_BASE +
19*cc3374acSPrasad Kummari 				    IOU_SCNTRS_BASE_FREQ_OFFSET);
20*cc3374acSPrasad Kummari 	if (counter_freq != 0U) {
21*cc3374acSPrasad Kummari 		ret = counter_freq;
22*cc3374acSPrasad Kummari 	} else {
23*cc3374acSPrasad Kummari 		INFO("Indicates counter frequency %dHz setting to %dHz\n",
24*cc3374acSPrasad Kummari 		     counter_freq, cpu_clock);
25*cc3374acSPrasad Kummari 		ret = cpu_clock;
26*cc3374acSPrasad Kummari 	}
27*cc3374acSPrasad Kummari 
28*cc3374acSPrasad Kummari 	return ret;
29*cc3374acSPrasad Kummari }
30*cc3374acSPrasad Kummari 
31f000744eSPrasad Kummari void set_cnt_freq(void)
32f000744eSPrasad Kummari {
33f000744eSPrasad Kummari 	uint64_t counter_freq;
34f000744eSPrasad Kummari 
35f000744eSPrasad Kummari 	/* Configure counter frequency */
36f000744eSPrasad Kummari 	counter_freq = read_cntfrq_el0();
37f000744eSPrasad Kummari 	if (counter_freq == 0U) {
38f000744eSPrasad Kummari 		write_cntfrq_el0(plat_get_syscnt_freq2());
39f000744eSPrasad Kummari 	}
40f000744eSPrasad Kummari }
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