121b14fd2SDhruva Gole /* 221b14fd2SDhruva Gole * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/ 3*8853eba6SDhruva Gole * k3low SoC specific bl31_setup 421b14fd2SDhruva Gole * 521b14fd2SDhruva Gole * SPDX-License-Identifier: BSD-3-Clause 621b14fd2SDhruva Gole */ 721b14fd2SDhruva Gole 821b14fd2SDhruva Gole #include <common/debug.h> 921b14fd2SDhruva Gole #include <ti_sci.h> 1021b14fd2SDhruva Gole #include <ti_sci_transport.h> 1121b14fd2SDhruva Gole 1221b14fd2SDhruva Gole #include <plat_private.h> 1321b14fd2SDhruva Gole 1421b14fd2SDhruva Gole /* Table of regions to map using the MMU */ 1521b14fd2SDhruva Gole const mmap_region_t plat_k3_mmap[] = { 16*8853eba6SDhruva Gole K3_MAP_REGION_FLAT(K3_USART_BASE, K3_USART_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 17*8853eba6SDhruva Gole K3_MAP_REGION_FLAT(K3_GIC_BASE, K3_GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 18*8853eba6SDhruva Gole K3_MAP_REGION_FLAT(K3_GTC_BASE, K3_GTC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 19*8853eba6SDhruva Gole K3_MAP_REGION_FLAT(TI_MAILBOX_TX_BASE, TI_MAILBOX_RX_TX_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 20*8853eba6SDhruva Gole K3_MAP_REGION_FLAT(WKUP_CTRL_MMR0_BASE, WKUP_CTRL_MMR0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 21*8853eba6SDhruva Gole K3_MAP_REGION_FLAT(MAILBOX_SHMEM_REGION_BASE, MAILBOX_SHMEM_REGION_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 2221b14fd2SDhruva Gole { /* sentinel */ } 2321b14fd2SDhruva Gole }; 2421b14fd2SDhruva Gole 2521b14fd2SDhruva Gole int ti_soc_init(void) 2621b14fd2SDhruva Gole { 27a5cf0ba4SDhruva Gole generic_delay_timer_init(); 2821b14fd2SDhruva Gole return 0; 2921b14fd2SDhruva Gole } 30