1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __BOARD_DEF_H__ 8 #define __BOARD_DEF_H__ 9 10 /* The ports must be in order and contiguous */ 11 #define K3_CLUSTER0_CORE_COUNT 2 12 #define K3_CLUSTER0_MSMC_PORT 0 13 14 #define K3_CLUSTER1_CORE_COUNT 2 15 #define K3_CLUSTER1_MSMC_PORT 1 16 17 #define K3_CLUSTER2_CORE_COUNT 2 18 #define K3_CLUSTER2_MSMC_PORT 2 19 20 #define K3_CLUSTER3_CORE_COUNT 2 21 #define K3_CLUSTER3_MSMC_PORT 3 22 23 /* 24 * This RAM will be used for the bootloader including code, bss, and stacks. 25 * It may need to be increased if BL31 grows in size. 26 */ 27 #define SEC_SRAM_BASE 0x70000000 /* Base of MSMC SRAM */ 28 #define SEC_SRAM_SIZE 0x00020000 /* 128k */ 29 30 #define PLAT_MAX_OFF_STATE 2 31 #define PLAT_MAX_RET_STATE 1 32 33 #endif /* __BOARD_DEF_H__ */ 34